DMA0_REGISTER_OFFSET 1717 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); DMA0_REGISTER_OFFSET 32 drivers/gpu/drm/amd/amdgpu/si_dma.c DMA0_REGISTER_OFFSET, DMA0_REGISTER_OFFSET 597 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 599 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); DMA0_REGISTER_OFFSET 602 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 604 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); DMA0_REGISTER_OFFSET 656 drivers/gpu/drm/amd/amdgpu/si_dma.c offset = DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 668 drivers/gpu/drm/amd/amdgpu/si_dma.c offset = DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 870 drivers/gpu/drm/radeon/ni.c case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): DMA0_REGISTER_OFFSET 1132 drivers/gpu/drm/radeon/ni.c WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); DMA0_REGISTER_OFFSET 1769 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 1850 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 1852 drivers/gpu/drm/radeon/ni.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); DMA0_REGISTER_OFFSET 62 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 86 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 107 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 166 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 168 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); DMA0_REGISTER_OFFSET 198 drivers/gpu/drm/radeon/ni_dma.c reg_offset = DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 1322 drivers/gpu/drm/radeon/si.c case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): DMA0_REGISTER_OFFSET 3282 drivers/gpu/drm/radeon/si.c WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); DMA0_REGISTER_OFFSET 3802 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 3884 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 3886 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); DMA0_REGISTER_OFFSET 4051 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); DMA0_REGISTER_OFFSET 4053 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); DMA0_REGISTER_OFFSET 5539 drivers/gpu/drm/radeon/si.c offset = DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 5551 drivers/gpu/drm/radeon/si.c offset = DMA0_REGISTER_OFFSET; DMA0_REGISTER_OFFSET 5958 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; DMA0_REGISTER_OFFSET 5959 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); DMA0_REGISTER_OFFSET 6074 drivers/gpu/drm/radeon/si.c dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; DMA0_REGISTER_OFFSET 6107 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);