DIVIL_MSR_REG 50 arch/mips/loongson64/common/cs5536/cs5536_acc.c _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); DIVIL_MSR_REG 55 arch/mips/loongson64/common/cs5536/cs5536_acc.c _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); DIVIL_MSR_REG 62 arch/mips/loongson64/common/cs5536/cs5536_ide.c _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); DIVIL_MSR_REG 64 arch/mips/loongson64/common/cs5536/cs5536_ide.c _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); DIVIL_MSR_REG 18 arch/mips/loongson64/common/cs5536/cs5536_isa.c DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO), DIVIL_MSR_REG 19 arch/mips/loongson64/common/cs5536/cs5536_isa.c DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ), DIVIL_MSR_REG 20 arch/mips/loongson64/common/cs5536/cs5536_isa.c DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI), DIVIL_MSR_REG 59 arch/mips/loongson64/common/cs5536/cs5536_isa.c _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); DIVIL_MSR_REG 61 arch/mips/loongson64/common/cs5536/cs5536_isa.c _wrmsr(DIVIL_MSR_REG(offset), hi, lo); DIVIL_MSR_REG 74 arch/mips/loongson64/common/cs5536/cs5536_isa.c _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); DIVIL_MSR_REG 76 arch/mips/loongson64/common/cs5536/cs5536_isa.c _wrmsr(DIVIL_MSR_REG(offset), hi, lo); DIVIL_MSR_REG 194 arch/mips/loongson64/common/cs5536/cs5536_isa.c _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); DIVIL_MSR_REG 199 arch/mips/loongson64/common/cs5536/cs5536_isa.c _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); DIVIL_MSR_REG 202 arch/mips/loongson64/common/cs5536/cs5536_isa.c _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); DIVIL_MSR_REG 207 arch/mips/loongson64/common/cs5536/cs5536_isa.c _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); DIVIL_MSR_REG 241 arch/mips/loongson64/common/cs5536/cs5536_isa.c _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); DIVIL_MSR_REG 93 arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); DIVIL_MSR_REG 127 arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100); DIVIL_MSR_REG 130 arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000); DIVIL_MSR_REG 133 arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); DIVIL_MSR_REG 59 arch/mips/loongson64/common/cs5536/cs5536_ohci.c _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); DIVIL_MSR_REG 63 arch/mips/loongson64/common/cs5536/cs5536_ohci.c _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); DIVIL_MSR_REG 136 arch/mips/loongson64/common/cs5536/cs5536_ohci.c _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); DIVIL_MSR_REG 45 arch/mips/loongson64/lemote-2f/reset.c _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); DIVIL_MSR_REG 47 arch/mips/loongson64/lemote-2f/reset.c _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); DIVIL_MSR_REG 57 arch/mips/loongson64/lemote-2f/reset.c _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);