DIV4_U            110 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
DIV4_U            142 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
DIV4_U            194 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
DIV4_U            113 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
DIV4_U            192 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
DIV4_U            115 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
DIV4_U            142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_URAM]  = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
DIV4_U            178 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
DIV4_U            116 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
DIV4_U            203 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
DIV4_U             76 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
DIV4_U            128 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),