DIV4_SH 111 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_SH 195 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 114 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_SH 145 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), DIV4_SH 193 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 116 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_SH 179 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 117 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4_SH 146 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), DIV4_SH 151 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), DIV4_SH 168 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0), DIV4_SH 173 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), DIV4_SH 204 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 155 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4_SH 208 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), DIV4_SH 212 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), DIV4_SH 248 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), DIV4_SH 269 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 71 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), DIV4_SH 109 arch/sh/kernel/cpu/sh4a/clock-sh7757.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 75 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), DIV4_SH 127 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 75 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), DIV4_SH 135 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), DIV4_SH 69 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), DIV4_SH 110 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),