DIV4_P 84 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT), DIV4_P 93 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */ DIV4_P 94 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */ DIV4_P 95 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */ DIV4_P 96 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */ DIV4_P 97 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */ DIV4_P 98 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */ DIV4_P 99 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */ DIV4_P 100 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */ DIV4_P 112 arch/sh/kernel/cpu/sh2a/clock-sh7264.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 114 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4_P 144 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), DIV4_P 145 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), DIV4_P 146 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), DIV4_P 147 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), DIV4_P 148 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), DIV4_P 149 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), DIV4_P 150 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 153 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), DIV4_P 154 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 155 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 156 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), DIV4_P 157 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), DIV4_P 158 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), DIV4_P 159 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), DIV4_P 160 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), DIV4_P 161 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), DIV4_P 163 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 164 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0), DIV4_P 166 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), DIV4_P 167 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), DIV4_P 168 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), DIV4_P 169 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), DIV4_P 170 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), DIV4_P 172 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), DIV4_P 173 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), DIV4_P 174 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), DIV4_P 198 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 117 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4_P 147 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), DIV4_P 148 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), DIV4_P 149 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), DIV4_P 150 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), DIV4_P 151 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), DIV4_P 152 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), DIV4_P 153 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 156 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), DIV4_P 157 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 158 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 159 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), DIV4_P 160 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), DIV4_P 161 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), DIV4_P 162 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), DIV4_P 164 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 166 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), DIV4_P 167 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), DIV4_P 168 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), DIV4_P 169 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), DIV4_P 170 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), DIV4_P 171 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), DIV4_P 172 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), DIV4_P 173 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), DIV4_P 196 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 119 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4_P 144 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 147 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 148 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 149 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0), DIV4_P 150 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), DIV4_P 152 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 155 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0), DIV4_P 157 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0), DIV4_P 166 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0), DIV4_P 182 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 120 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), DIV4_P 152 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), DIV4_P 154 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 158 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), DIV4_P 159 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 160 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 161 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 162 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 170 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 174 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0), DIV4_P 176 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), DIV4_P 207 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 157 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), DIV4_P 210 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), DIV4_P 213 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), DIV4_P 215 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 219 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 220 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 221 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 222 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 231 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 232 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), DIV4_P 238 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), DIV4_P 271 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 78 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT), DIV4_P 126 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), DIV4_P 127 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), DIV4_P 128 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), DIV4_P 129 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), DIV4_P 130 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), DIV4_P 131 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), DIV4_P 132 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), DIV4_P 133 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), DIV4_P 134 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), DIV4_P 135 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), DIV4_P 136 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 137 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), DIV4_P 138 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), DIV4_P 139 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), DIV4_P 140 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 141 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 142 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 143 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), DIV4_P 146 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), DIV4_P 147 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), DIV4_P 148 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), DIV4_P 149 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), DIV4_P 150 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), DIV4_P 151 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0), DIV4_P 152 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0), DIV4_P 153 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), DIV4_P 154 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), DIV4_P 157 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0), DIV4_P 158 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0), DIV4_P 159 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), DIV4_P 160 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), DIV4_P 161 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), DIV4_P 162 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), DIV4_P 163 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0), DIV4_P 164 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0), DIV4_P 165 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0), DIV4_P 166 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0), DIV4_P 167 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0), DIV4_P 168 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0), DIV4_P 169 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0), DIV4_P 170 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0), DIV4_P 171 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0), DIV4_P 172 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0), DIV4_P 173 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0), DIV4_P 174 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0), DIV4_P 175 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0), DIV4_P 189 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 70 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), DIV4_P 85 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), DIV4_P 86 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), DIV4_P 89 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0), DIV4_P 90 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), DIV4_P 91 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), DIV4_P 92 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), DIV4_P 93 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), DIV4_P 94 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), DIV4_P 95 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), DIV4_P 96 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), DIV4_P 99 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), DIV4_P 108 arch/sh/kernel/cpu/sh4a/clock-sh7757.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 70 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_P] = DIV4(0, 0x0f80, 0), DIV4_P 91 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), DIV4_P 92 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), DIV4_P 93 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), DIV4_P 94 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), DIV4_P 95 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), DIV4_P 96 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), DIV4_P 97 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), DIV4_P 98 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), DIV4_P 99 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), DIV4_P 100 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), DIV4_P 101 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), DIV4_P 102 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), DIV4_P 103 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 104 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 105 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), DIV4_P 106 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), DIV4_P 122 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 71 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_P] = DIV4(0, 0x0b40, 0), DIV4_P 92 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), DIV4_P 93 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), DIV4_P 94 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), DIV4_P 95 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), DIV4_P 96 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), DIV4_P 97 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), DIV4_P 98 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), DIV4_P 99 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), DIV4_P 100 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), DIV4_P 101 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), DIV4_P 102 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), DIV4_P 103 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), DIV4_P 104 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), DIV4_P 105 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), DIV4_P 106 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), DIV4_P 107 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), DIV4_P 108 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 109 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 110 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), DIV4_P 111 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), DIV4_P 112 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), DIV4_P 131 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), DIV4_P 65 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_P] = DIV4(0, 0x0f80, 0), DIV4_P 83 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), DIV4_P 84 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), DIV4_P 85 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), DIV4_P 86 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), DIV4_P 87 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), DIV4_P 88 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), DIV4_P 89 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), DIV4_P 90 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), DIV4_P 91 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0), DIV4_P 92 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), DIV4_P 106 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),