DIV4_M1 158 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4_M1 272 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),