DIV4_I             82 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 	[DIV4_I] = DIV4(FRQCR, 4, 0x7,  CLK_ENABLE_REG_16BIT
DIV4_I            111 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            110 arch/sh/kernel/cpu/sh2a/clock-sh7269.c 	[DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
DIV4_I            146 arch/sh/kernel/cpu/sh2a/clock-sh7269.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            109 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
DIV4_I            139 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
DIV4_I            140 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
DIV4_I            141 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
DIV4_I            193 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            112 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
DIV4_I            142 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
DIV4_I            143 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
DIV4_I            144 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
DIV4_I            191 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            114 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
DIV4_I            177 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            115 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
DIV4_I            143 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TLB]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 31, CLK_ENABLE_ON_INIT),
DIV4_I            144 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_IC]     = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 30, CLK_ENABLE_ON_INIT),
DIV4_I            145 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_OC]     = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 29, CLK_ENABLE_ON_INIT),
DIV4_I            147 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_ILMEM]  = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 27, CLK_ENABLE_ON_INIT),
DIV4_I            148 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_FPU]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 24, CLK_ENABLE_ON_INIT),
DIV4_I            149 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_INTC]   = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 22, CLK_ENABLE_ON_INIT),
DIV4_I            153 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_UBC]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 17, 0),
DIV4_I            202 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I            154 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
DIV4_I            203 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 31, CLK_ENABLE_ON_INIT),
DIV4_I            204 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 30, CLK_ENABLE_ON_INIT),
DIV4_I            205 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 29, CLK_ENABLE_ON_INIT),
DIV4_I            207 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I],   MSTPCR0, 27, CLK_ENABLE_ON_INIT),
DIV4_I            209 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 24, CLK_ENABLE_ON_INIT),
DIV4_I            214 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],     MSTPCR0, 17, 0),
DIV4_I            268 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I             73 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
DIV4_I            184 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I             72 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
DIV4_I            110 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I             77 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
DIV4_I            129 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I             76 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
DIV4_I            136 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
DIV4_I             70 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
DIV4_I            111 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),