DIV4_DDR           73 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
DIV4_DDR          125 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
DIV4_DDR           73 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
DIV4_DDR          133 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
DIV4_DDR           67 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
DIV4_DDR          108 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),