DIV4_B 112 arch/sh/kernel/cpu/sh2a/clock-sh7269.c [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT DIV4_B 147 arch/sh/kernel/cpu/sh2a/clock-sh7269.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 112 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_B 143 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), DIV4_B 175 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), DIV4_B 176 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), DIV4_B 177 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), DIV4_B 178 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), DIV4_B 179 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), DIV4_B 180 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), DIV4_B 181 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), DIV4_B 182 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), DIV4_B 196 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 115 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_B 146 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), DIV4_B 174 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), DIV4_B 175 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), DIV4_B 176 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), DIV4_B 177 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), DIV4_B 178 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), DIV4_B 179 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), DIV4_B 180 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), DIV4_B 194 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 117 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4_B 143 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), DIV4_B 158 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), DIV4_B 159 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), DIV4_B 160 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), DIV4_B 161 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), DIV4_B 162 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), DIV4_B 163 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), DIV4_B 164 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), DIV4_B 165 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), DIV4_B 180 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 118 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4_B 150 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), DIV4_B 157 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), DIV4_B 163 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), DIV4_B 164 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), DIV4_B 165 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), DIV4_B 166 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), DIV4_B 167 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), DIV4_B 175 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), DIV4_B 177 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), DIV4_B 178 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), DIV4_B 179 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), DIV4_B 180 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), DIV4_B 182 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0), DIV4_B 183 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0), DIV4_B 184 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), DIV4_B 185 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), DIV4_B 186 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), DIV4_B 187 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), DIV4_B 188 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), DIV4_B 189 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), DIV4_B 190 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), DIV4_B 191 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), DIV4_B 205 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 156 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4_B 206 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), DIV4_B 211 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), DIV4_B 218 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), DIV4_B 223 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), DIV4_B 224 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), DIV4_B 225 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), DIV4_B 226 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), DIV4_B 227 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), DIV4_B 234 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), DIV4_B 235 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), DIV4_B 236 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), DIV4_B 237 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), DIV4_B 239 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), DIV4_B 240 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), DIV4_B 241 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), DIV4_B 242 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), DIV4_B 243 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), DIV4_B 244 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), DIV4_B 245 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), DIV4_B 246 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), DIV4_B 247 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), DIV4_B 249 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), DIV4_B 250 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), DIV4_B 251 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), DIV4_B 252 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), DIV4_B 253 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), DIV4_B 254 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), DIV4_B 255 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), DIV4_B 256 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), DIV4_B 270 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 75 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT), DIV4_B 187 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 74 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), DIV4_B 126 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 74 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), DIV4_B 134 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), DIV4_B 68 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), DIV4_B 109 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),