DIV4 82 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT DIV4 84 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT), DIV4 110 arch/sh/kernel/cpu/sh2a/clock-sh7269.c [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT DIV4 112 arch/sh/kernel/cpu/sh2a/clock-sh7269.c [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT DIV4 109 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 110 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 111 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 112 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 113 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 114 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4 115 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), DIV4 116 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), DIV4 112 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), DIV4 113 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 114 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 115 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 116 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 117 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4 118 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), DIV4 119 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), DIV4 114 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), DIV4 115 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 116 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 117 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 118 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), DIV4 119 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), DIV4 125 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0), DIV4 131 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), DIV4 132 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), DIV4 115 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4 116 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4 117 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4 118 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), DIV4 119 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), DIV4 120 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), DIV4 126 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), DIV4 132 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), DIV4 133 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0), DIV4 154 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), DIV4 155 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4 156 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4 157 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), DIV4 158 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), DIV4 73 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT), DIV4 74 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT), DIV4 75 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT), DIV4 76 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT), DIV4 77 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT), DIV4 78 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT), DIV4 70 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), DIV4 71 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), DIV4 72 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), DIV4 70 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_P] = DIV4(0, 0x0f80, 0), DIV4 71 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_DU] = DIV4(4, 0x0ff0, 0), DIV4 72 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_GA] = DIV4(8, 0x0030, 0), DIV4 73 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), DIV4 74 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), DIV4 75 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), DIV4 76 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), DIV4 77 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), DIV4 71 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_P] = DIV4(0, 0x0b40, 0), DIV4 72 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_DU] = DIV4(4, 0x0010, 0), DIV4 73 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT), DIV4 74 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), DIV4 75 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), DIV4 76 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT), DIV4 65 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_P] = DIV4(0, 0x0f80, 0), DIV4 66 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_SHA] = DIV4(4, 0x0ff0, 0), DIV4 67 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), DIV4 68 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), DIV4 69 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), DIV4 70 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), DIV4 169 drivers/video/fbdev/platinumfb.h {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }} DIV4 181 drivers/video/fbdev/platinumfb.h {{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }} DIV4 193 drivers/video/fbdev/platinumfb.h {{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }} DIV4 205 drivers/video/fbdev/platinumfb.h {{ 54, 3 + DIV4 }, { 95, 1 + DIV8 }} DIV4 217 drivers/video/fbdev/platinumfb.h {{ 54, 3 + DIV4 }, { 88, 1 + DIV8 }} DIV4 241 drivers/video/fbdev/platinumfb.h {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }} DIV4 253 drivers/video/fbdev/platinumfb.h {{ 99, 4 + DIV8 }, { 42, 5 + DIV4 }} DIV4 265 drivers/video/fbdev/platinumfb.h {{ 26, 0 + DIV8 }, { 14, 2 + DIV4 }}