DISPLAY_MMIO_BASE 253 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) DISPLAY_MMIO_BASE 256 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) DISPLAY_MMIO_BASE 260 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) DISPLAY_MMIO_BASE 3254 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) DISPLAY_MMIO_BASE 3255 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) DISPLAY_MMIO_BASE 3256 drivers/gpu/drm/i915/i915_reg.h #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) DISPLAY_MMIO_BASE 3353 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) DISPLAY_MMIO_BASE 3354 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) DISPLAY_MMIO_BASE 3355 drivers/gpu/drm/i915/i915_reg.h #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) DISPLAY_MMIO_BASE 3427 drivers/gpu/drm/i915/i915_reg.h #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) DISPLAY_MMIO_BASE 3567 drivers/gpu/drm/i915/i915_reg.h #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ DISPLAY_MMIO_BASE 4390 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) DISPLAY_MMIO_BASE 4420 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) DISPLAY_MMIO_BASE 4502 drivers/gpu/drm/i915/i915_reg.h #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) DISPLAY_MMIO_BASE 4777 drivers/gpu/drm/i915/i915_reg.h #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) DISPLAY_MMIO_BASE 4795 drivers/gpu/drm/i915/i915_reg.h #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) DISPLAY_MMIO_BASE 4807 drivers/gpu/drm/i915/i915_reg.h #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) DISPLAY_MMIO_BASE 4809 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) DISPLAY_MMIO_BASE 4810 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) DISPLAY_MMIO_BASE 4814 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) DISPLAY_MMIO_BASE 4815 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) DISPLAY_MMIO_BASE 4819 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) DISPLAY_MMIO_BASE 4820 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) DISPLAY_MMIO_BASE 4825 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ DISPLAY_MMIO_BASE 4848 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) DISPLAY_MMIO_BASE 4870 drivers/gpu/drm/i915/i915_reg.h #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) DISPLAY_MMIO_BASE 5495 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) DISPLAY_MMIO_BASE 5496 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) DISPLAY_MMIO_BASE 5497 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) DISPLAY_MMIO_BASE 5498 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) DISPLAY_MMIO_BASE 5499 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) DISPLAY_MMIO_BASE 5500 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) DISPLAY_MMIO_BASE 5502 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) DISPLAY_MMIO_BASE 5503 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) DISPLAY_MMIO_BASE 5504 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) DISPLAY_MMIO_BASE 5505 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) DISPLAY_MMIO_BASE 5506 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) DISPLAY_MMIO_BASE 5507 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) DISPLAY_MMIO_BASE 5509 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) DISPLAY_MMIO_BASE 5510 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) DISPLAY_MMIO_BASE 5511 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) DISPLAY_MMIO_BASE 5512 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) DISPLAY_MMIO_BASE 5513 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) DISPLAY_MMIO_BASE 5514 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) DISPLAY_MMIO_BASE 5516 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) DISPLAY_MMIO_BASE 5517 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) DISPLAY_MMIO_BASE 5518 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) DISPLAY_MMIO_BASE 5519 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) DISPLAY_MMIO_BASE 5520 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) DISPLAY_MMIO_BASE 5521 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) DISPLAY_MMIO_BASE 5523 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) DISPLAY_MMIO_BASE 5524 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) DISPLAY_MMIO_BASE 5525 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) DISPLAY_MMIO_BASE 5526 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) DISPLAY_MMIO_BASE 5527 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) DISPLAY_MMIO_BASE 5528 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) DISPLAY_MMIO_BASE 5530 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) DISPLAY_MMIO_BASE 5531 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) DISPLAY_MMIO_BASE 5532 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) DISPLAY_MMIO_BASE 5533 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) DISPLAY_MMIO_BASE 5534 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) DISPLAY_MMIO_BASE 5535 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) DISPLAY_MMIO_BASE 5829 drivers/gpu/drm/i915/i915_reg.h #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) DISPLAY_MMIO_BASE 5864 drivers/gpu/drm/i915/i915_reg.h #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) DISPLAY_MMIO_BASE 5875 drivers/gpu/drm/i915/i915_reg.h #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) DISPLAY_MMIO_BASE 5891 drivers/gpu/drm/i915/i915_reg.h #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) DISPLAY_MMIO_BASE 6310 drivers/gpu/drm/i915/i915_reg.h #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) DISPLAY_MMIO_BASE 6311 drivers/gpu/drm/i915/i915_reg.h #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) DISPLAY_MMIO_BASE 6312 drivers/gpu/drm/i915/i915_reg.h #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) DISPLAY_MMIO_BASE 6316 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) DISPLAY_MMIO_BASE 6317 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) DISPLAY_MMIO_BASE 6318 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) DISPLAY_MMIO_BASE 6321 drivers/gpu/drm/i915/i915_reg.h #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) DISPLAY_MMIO_BASE 6322 drivers/gpu/drm/i915/i915_reg.h #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) DISPLAY_MMIO_BASE 6326 drivers/gpu/drm/i915/i915_reg.h #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) DISPLAY_MMIO_BASE 6331 drivers/gpu/drm/i915/i915_reg.h #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) DISPLAY_MMIO_BASE 6332 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) DISPLAY_MMIO_BASE 6333 drivers/gpu/drm/i915/i915_reg.h #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) DISPLAY_MMIO_BASE 6334 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) DISPLAY_MMIO_BASE 6335 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) DISPLAY_MMIO_BASE 6336 drivers/gpu/drm/i915/i915_reg.h #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) DISPLAY_MMIO_BASE 6337 drivers/gpu/drm/i915/i915_reg.h #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) DISPLAY_MMIO_BASE 6338 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) DISPLAY_MMIO_BASE 8990 drivers/gpu/drm/i915/i915_reg.h #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)