DISPC_IRQ_GFX_FIFO_UNDERFLOW 166 drivers/gpu/drm/omapdrm/omap_irq.c { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, DISPC_IRQ_GFX_FIFO_UNDERFLOW 172 drivers/gpu/drm/omapdrm/omap_irq.c const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW DISPC_IRQ_GFX_FIFO_UNDERFLOW 252 drivers/gpu/drm/omapdrm/omap_irq.c [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, DISPC_IRQ_GFX_FIFO_UNDERFLOW 24 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ DISPC_IRQ_GFX_FIFO_UNDERFLOW 329 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c DISPC_IRQ_GFX_FIFO_UNDERFLOW,