DISPC_CONTROL     299 arch/arm/mach-omap2/display.c 	v = omap_hwmod_read(oh, DISPC_CONTROL);
DISPC_CONTROL     346 arch/arm/mach-omap2/display.c 	v = omap_hwmod_read(oh, DISPC_CONTROL);
DISPC_CONTROL     348 arch/arm/mach-omap2/display.c 	omap_hwmod_write(v, oh, DISPC_CONTROL);
DISPC_CONTROL     262 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_ENABLE]		= { DISPC_CONTROL,  0,  0 },
DISPC_CONTROL     263 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_STNTFT]		= { DISPC_CONTROL,  3,  3 },
DISPC_CONTROL     264 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_GO]		= { DISPC_CONTROL,  5,  5 },
DISPC_CONTROL     265 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_TFTDATALINES]	= { DISPC_CONTROL,  9,  8 },
DISPC_CONTROL     266 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_STALLMODE]	= { DISPC_CONTROL, 11, 11 },
DISPC_CONTROL     285 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_ENABLE]		= { DISPC_CONTROL,  1,  1 },
DISPC_CONTROL     287 drivers/gpu/drm/omapdrm/dss/dispc.c 			[DISPC_MGR_FLD_GO]		= { DISPC_CONTROL,  6,  6 },
DISPC_CONTROL     380 drivers/gpu/drm/omapdrm/dss/dispc.c 	const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
DISPC_CONTROL    2893 drivers/gpu/drm/omapdrm/dss/dispc.c 	REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
DISPC_CONTROL    2901 drivers/gpu/drm/omapdrm/dss/dispc.c 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
DISPC_CONTROL    2909 drivers/gpu/drm/omapdrm/dss/dispc.c 	REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
DISPC_CONTROL    3035 drivers/gpu/drm/omapdrm/dss/dispc.c 	l = dispc_read_reg(dispc, DISPC_CONTROL);
DISPC_CONTROL    3038 drivers/gpu/drm/omapdrm/dss/dispc.c 	dispc_write_reg(dispc, DISPC_CONTROL, l);
DISPC_CONTROL    3251 drivers/gpu/drm/omapdrm/dss/dispc.c 			REG_FLD_MOD(dispc, DISPC_CONTROL,
DISPC_CONTROL    3482 drivers/gpu/drm/omapdrm/dss/dispc.c 	DUMPREG(dispc, DISPC_CONTROL);
DISPC_CONTROL     174 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_ENABLE]		= { DISPC_CONTROL,  0,  0 },
DISPC_CONTROL     175 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_STNTFT]		= { DISPC_CONTROL,  3,  3 },
DISPC_CONTROL     176 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_GO]		= { DISPC_CONTROL,  5,  5 },
DISPC_CONTROL     177 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_TFTDATALINES]	= { DISPC_CONTROL,  9,  8 },
DISPC_CONTROL     178 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_STALLMODE]	= { DISPC_CONTROL, 11, 11 },
DISPC_CONTROL     191 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_ENABLE]		= { DISPC_CONTROL,  1,  1 },
DISPC_CONTROL     193 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 			[DISPC_MGR_FLD_GO]		= { DISPC_CONTROL,  6,  6 },
DISPC_CONTROL     270 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
DISPC_CONTROL    2921 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
DISPC_CONTROL    2929 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
DISPC_CONTROL    2937 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
DISPC_CONTROL    3051 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	l = dispc_read_reg(DISPC_CONTROL);
DISPC_CONTROL    3054 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	dispc_write_reg(DISPC_CONTROL, l);
DISPC_CONTROL    3522 drivers/video/fbdev/omap2/omapfb/dss/dispc.c 	DUMPREG(DISPC_CONTROL);