DIMMS_PER_CHANNEL  340 drivers/edac/i5400_edac.c 	u16 b0_mtr[DIMMS_PER_CHANNEL];	/* Memory Technlogy Reg */
DIMMS_PER_CHANNEL  344 drivers/edac/i5400_edac.c 	u16 b1_mtr[DIMMS_PER_CHANNEL];	/* Memory Technlogy Reg */
DIMMS_PER_CHANNEL  349 drivers/edac/i5400_edac.c 	struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];
DIMMS_PER_CHANNEL  871 drivers/edac/i5400_edac.c 	if (n >= DIMMS_PER_CHANNEL) {
DIMMS_PER_CHANNEL 1100 drivers/edac/i5400_edac.c 	for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {
DIMMS_PER_CHANNEL 1125 drivers/edac/i5400_edac.c 	for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
DIMMS_PER_CHANNEL 1142 drivers/edac/i5400_edac.c 		for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
DIMMS_PER_CHANNEL 1291 drivers/edac/i5400_edac.c 	layers[2].size = DIMMS_PER_CHANNEL;
DIMMS_PER_CHANNEL 1304 drivers/edac/i5400_edac.c 	pvt->maxdimmperch = DIMMS_PER_CHANNEL;