DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 187 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 329 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 471 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 615 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 799 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 224 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },