DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  230 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	{   ixDIDT_TCP_CTRL0,                   DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,                   DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT,                 0x0000,     GPU_CONFIGREG_DIDT_IND },
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  372 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	{   ixDIDT_TCP_CTRL0,                   DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,                   DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT,                 0x0000,     GPU_CONFIGREG_DIDT_IND },
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  514 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	{   ixDIDT_TCP_CTRL0,                   DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,                   DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT,                 0x0000,     GPU_CONFIGREG_DIDT_IND },
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  659 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	{   ixDIDT_TCP_CTRL0,                   DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,                   DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT,                 0x0000,     GPU_CONFIGREG_DIDT_IND },
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  844 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c     {   ixDIDT_TCP_CTRL0,                   DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,                   DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT,                 0x0000,     GPU_CONFIGREG_DIDT_IND },
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT  236 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	{  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,  DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },