DEF_INT_MASK      389 drivers/net/ethernet/hisilicon/hip04_eth.c 	priv->reg_inten = DEF_INT_MASK;
DEF_INT_MASK      399 drivers/net/ethernet/hisilicon/hip04_eth.c 	priv->reg_inten &= ~(DEF_INT_MASK);
DEF_INT_MASK      561 drivers/net/ethernet/hisilicon/hip04_eth.c 			writel_relaxed(DEF_INT_MASK & ~RCV_INT,
DEF_INT_MASK      671 drivers/net/ethernet/hisilicon/hip04_eth.c 	writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
DEF_INT_MASK      688 drivers/net/ethernet/hisilicon/hip04_eth.c 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
DEF_INT_MASK      705 drivers/net/ethernet/hisilicon/hip04_eth.c 		writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
DEF_INT_MASK      316 drivers/net/ethernet/hisilicon/hisi_femac.c 		writel(ints & DEF_INT_MASK,
DEF_INT_MASK      318 drivers/net/ethernet/hisilicon/hisi_femac.c 	} while (ints & DEF_INT_MASK);
DEF_INT_MASK      322 drivers/net/ethernet/hisilicon/hisi_femac.c 		hisi_femac_irq_enable(priv, DEF_INT_MASK &
DEF_INT_MASK      337 drivers/net/ethernet/hisilicon/hisi_femac.c 	if (likely(ints & DEF_INT_MASK)) {
DEF_INT_MASK      338 drivers/net/ethernet/hisilicon/hisi_femac.c 		writel(ints & DEF_INT_MASK,
DEF_INT_MASK      340 drivers/net/ethernet/hisilicon/hisi_femac.c 		hisi_femac_irq_disable(priv, DEF_INT_MASK);
DEF_INT_MASK      477 drivers/net/ethernet/hisilicon/hisi_femac.c 	hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);
DEF_INT_MASK      409 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c 	writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);
DEF_INT_MASK      658 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c 	} while (ints & DEF_INT_MASK);
DEF_INT_MASK      675 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c 	if (likely(ints & DEF_INT_MASK)) {