DEC_CPU_IRQ_MASK  103 arch/mips/dec/setup.c int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
DEC_CPU_IRQ_MASK  220 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
DEC_CPU_IRQ_MASK  222 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
DEC_CPU_IRQ_MASK  224 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
DEC_CPU_IRQ_MASK  226 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
DEC_CPU_IRQ_MASK  228 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
DEC_CPU_IRQ_MASK  297 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
DEC_CPU_IRQ_MASK  299 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
DEC_CPU_IRQ_MASK  301 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
DEC_CPU_IRQ_MASK  303 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
DEC_CPU_IRQ_MASK  372 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
DEC_CPU_IRQ_MASK  374 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
DEC_CPU_IRQ_MASK  376 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
DEC_CPU_IRQ_MASK  469 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
DEC_CPU_IRQ_MASK  471 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
DEC_CPU_IRQ_MASK  473 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
DEC_CPU_IRQ_MASK  475 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
DEC_CPU_IRQ_MASK  570 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
DEC_CPU_IRQ_MASK  572 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
DEC_CPU_IRQ_MASK  574 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
DEC_CPU_IRQ_MASK  667 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
DEC_CPU_IRQ_MASK  669 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
DEC_CPU_IRQ_MASK  671 arch/mips/dec/setup.c 	{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },