DDRECC            926 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	INTC_VECT(DDRECC, 0x2620),
DDRECC           1002 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	    DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
DDRECC           1100 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	{ INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },