DDC_DDCMD0        119 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
DDC_DDCMD0        169 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 				offset = DDC_DDCMD0;
DDC_DDCMD0        191 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
DDC_DDCMD0        192 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);