DDC_DDCMCTL1      103 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
DDC_DDCMCTL1      105 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
DDC_DDCMCTL1      106 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
DDC_DDCMCTL1      120 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
DDC_DDCMCTL1      123 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
DDC_DDCMCTL1      144 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 		sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
DDC_DDCMCTL1      150 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 		ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
DDC_DDCMCTL1      193 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
DDC_DDCMCTL1      197 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
DDC_DDCMCTL1      225 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {