DDC_DDCMCTL0      221 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
DDC_DDCMCTL0      222 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
DDC_DDCMCTL0      223 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
DDC_DDCMCTL0      230 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,