DDCM_PGLEN_OFFSET  120 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
DDCM_PGLEN_OFFSET  145 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 			       DDCM_PGLEN_OFFSET, read_count - 1);
DDCM_PGLEN_OFFSET  193 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,