DC_WR_CH_CONF 212 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 217 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 245 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 247 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 255 drivers/gpu/ipu-v3/ipu-dc.c val = readl(dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 257 drivers/gpu/ipu-v3/ipu-dc.c writel(val, dc->base + DC_WR_CH_CONF); DC_WR_CH_CONF 367 drivers/gpu/ipu-v3/ipu-dc.c priv->channels[1].base + DC_WR_CH_CONF); DC_WR_CH_CONF 369 drivers/gpu/ipu-v3/ipu-dc.c priv->channels[5].base + DC_WR_CH_CONF);