DC_STATE_EN_UPTO_DC5 642 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, DC_STATE_EN_UPTO_DC5 663 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, DC_STATE_EN_UPTO_DC5 716 drivers/gpu/drm/i915/display/intel_display_power.c mask = DC_STATE_EN_UPTO_DC5; DC_STATE_EN_UPTO_DC5 849 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), DC_STATE_EN_UPTO_DC5 867 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); DC_STATE_EN_UPTO_DC5 1004 drivers/gpu/drm/i915/display/intel_display_power.c else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) DC_STATE_EN_UPTO_DC5 3972 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_UPTO_DC5; DC_STATE_EN_UPTO_DC5 5229 drivers/gpu/drm/i915/display/intel_display_power.c DC_STATE_EN_UPTO_DC5) DC_STATE_EN_UPTO_DC5 5236 drivers/gpu/drm/i915/display/intel_display_power.c (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))