DC_STATE_EN       640 drivers/gpu/drm/i915/display/intel_display_power.c 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
DC_STATE_EN       642 drivers/gpu/drm/i915/display/intel_display_power.c 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
DC_STATE_EN       663 drivers/gpu/drm/i915/display/intel_display_power.c 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
DC_STATE_EN       682 drivers/gpu/drm/i915/display/intel_display_power.c 	I915_WRITE(DC_STATE_EN, state);
DC_STATE_EN       690 drivers/gpu/drm/i915/display/intel_display_power.c 		v = I915_READ(DC_STATE_EN);
DC_STATE_EN       693 drivers/gpu/drm/i915/display/intel_display_power.c 			I915_WRITE(DC_STATE_EN, state);
DC_STATE_EN       731 drivers/gpu/drm/i915/display/intel_display_power.c 	val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
DC_STATE_EN       769 drivers/gpu/drm/i915/display/intel_display_power.c 	val = I915_READ(DC_STATE_EN);
DC_STATE_EN       849 drivers/gpu/drm/i915/display/intel_display_power.c 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
DC_STATE_EN       874 drivers/gpu/drm/i915/display/intel_display_power.c 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
DC_STATE_EN       954 drivers/gpu/drm/i915/display/intel_display_power.c 	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
DC_STATE_EN      2893 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(DC_STATE_EN, D_SKL_PLUS);