DC_HPD1_INT_CONTROL   61 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		DC_HPD1_INT_CONTROL,
DC_HPD1_INT_CONTROL 6924 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
DC_HPD1_INT_CONTROL 6925 drivers/gpu/drm/radeon/cik.c 	WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL 7056 drivers/gpu/drm/radeon/cik.c 	hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
DC_HPD1_INT_CONTROL 7278 drivers/gpu/drm/radeon/cik.c 	WREG32(DC_HPD1_INT_CONTROL, hpd1);
DC_HPD1_INT_CONTROL 7379 drivers/gpu/drm/radeon/cik.c 		tmp = RREG32(DC_HPD1_INT_CONTROL);
DC_HPD1_INT_CONTROL 7381 drivers/gpu/drm/radeon/cik.c 		WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL 7409 drivers/gpu/drm/radeon/cik.c 		tmp = RREG32(DC_HPD1_INT_CONTROL);
DC_HPD1_INT_CONTROL 7411 drivers/gpu/drm/radeon/cik.c 		WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL   43 drivers/gpu/drm/radeon/evergreen.c #define DC_HPDx_INT_CONTROL(x)    (DC_HPD1_INT_CONTROL + (x * 0xc))
DC_HPD1_INT_CONTROL  868 drivers/gpu/drm/radeon/r600.c 			tmp = RREG32(DC_HPD1_INT_CONTROL);
DC_HPD1_INT_CONTROL  873 drivers/gpu/drm/radeon/r600.c 			WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL 3635 drivers/gpu/drm/radeon/r600.c 		tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
DC_HPD1_INT_CONTROL 3636 drivers/gpu/drm/radeon/r600.c 		WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL 3787 drivers/gpu/drm/radeon/r600.c 		hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
DC_HPD1_INT_CONTROL 3883 drivers/gpu/drm/radeon/r600.c 		WREG32(DC_HPD1_INT_CONTROL, hpd1);
DC_HPD1_INT_CONTROL 3954 drivers/gpu/drm/radeon/r600.c 			tmp = RREG32(DC_HPD1_INT_CONTROL);
DC_HPD1_INT_CONTROL 3956 drivers/gpu/drm/radeon/r600.c 			WREG32(DC_HPD1_INT_CONTROL, tmp);
DC_HPD1_INT_CONTROL  167 drivers/gpu/drm/radeon/si.c #define DC_HPDx_INT_CONTROL(x)    (DC_HPD1_INT_CONTROL + (x * 0xc))