DC_CMD_STATE_CONTROL  116 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  117 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL 1227 drivers/gpu/drm/tegra/dc.c 	DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
DC_CMD_STATE_CONTROL 1918 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL 1919 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL 1922 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL 1923 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  172 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  177 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  192 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  197 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  673 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  674 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  675 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
DC_CMD_STATE_CONTROL  676 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);