DC21285_IO 25 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCICMD DC21285_IO(0x0004) DC21285_IO 26 arch/arm/include/asm/hardware/dec21285.h #define CSR_CLASSREV DC21285_IO(0x0008) DC21285_IO 27 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCICACHELINESIZE DC21285_IO(0x000c) DC21285_IO 28 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCICSRBASE DC21285_IO(0x0010) DC21285_IO 29 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCICSRIOBASE DC21285_IO(0x0014) DC21285_IO 30 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCISDRAMBASE DC21285_IO(0x0018) DC21285_IO 31 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCIROMBASE DC21285_IO(0x0030) DC21285_IO 32 arch/arm/include/asm/hardware/dec21285.h #define CSR_MBOX0 DC21285_IO(0x0050) DC21285_IO 33 arch/arm/include/asm/hardware/dec21285.h #define CSR_MBOX1 DC21285_IO(0x0054) DC21285_IO 34 arch/arm/include/asm/hardware/dec21285.h #define CSR_MBOX2 DC21285_IO(0x0058) DC21285_IO 35 arch/arm/include/asm/hardware/dec21285.h #define CSR_MBOX3 DC21285_IO(0x005c) DC21285_IO 36 arch/arm/include/asm/hardware/dec21285.h #define CSR_DOORBELL DC21285_IO(0x0060) DC21285_IO 37 arch/arm/include/asm/hardware/dec21285.h #define CSR_DOORBELL_SETUP DC21285_IO(0x0064) DC21285_IO 38 arch/arm/include/asm/hardware/dec21285.h #define CSR_ROMWRITEREG DC21285_IO(0x0068) DC21285_IO 39 arch/arm/include/asm/hardware/dec21285.h #define CSR_CSRBASEMASK DC21285_IO(0x00f8) DC21285_IO 40 arch/arm/include/asm/hardware/dec21285.h #define CSR_CSRBASEOFFSET DC21285_IO(0x00fc) DC21285_IO 41 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMBASEMASK DC21285_IO(0x0100) DC21285_IO 42 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104) DC21285_IO 43 arch/arm/include/asm/hardware/dec21285.h #define CSR_ROMBASEMASK DC21285_IO(0x0108) DC21285_IO 44 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMTIMING DC21285_IO(0x010c) DC21285_IO 45 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110) DC21285_IO 46 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114) DC21285_IO 47 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118) DC21285_IO 48 arch/arm/include/asm/hardware/dec21285.h #define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c) DC21285_IO 49 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_INFREEHEAD DC21285_IO(0x0120) DC21285_IO 50 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124) DC21285_IO 51 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128) DC21285_IO 52 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c) DC21285_IO 53 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_INFREECOUNT DC21285_IO(0x0130) DC21285_IO 54 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134) DC21285_IO 55 arch/arm/include/asm/hardware/dec21285.h #define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138) DC21285_IO 56 arch/arm/include/asm/hardware/dec21285.h #define CSR_SA110_CNTL DC21285_IO(0x013c) DC21285_IO 97 arch/arm/include/asm/hardware/dec21285.h #define CSR_PCIADDR_EXTN DC21285_IO(0x0140) DC21285_IO 98 arch/arm/include/asm/hardware/dec21285.h #define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144) DC21285_IO 99 arch/arm/include/asm/hardware/dec21285.h #define CSR_XBUS_CYCLE DC21285_IO(0x0148) DC21285_IO 100 arch/arm/include/asm/hardware/dec21285.h #define CSR_XBUS_IOSTROBE DC21285_IO(0x014c) DC21285_IO 101 arch/arm/include/asm/hardware/dec21285.h #define CSR_DOORBELL_PCI DC21285_IO(0x0150) DC21285_IO 102 arch/arm/include/asm/hardware/dec21285.h #define CSR_DOORBELL_SA110 DC21285_IO(0x0154) DC21285_IO 103 arch/arm/include/asm/hardware/dec21285.h #define CSR_UARTDR DC21285_IO(0x0160) DC21285_IO 104 arch/arm/include/asm/hardware/dec21285.h #define CSR_RXSTAT DC21285_IO(0x0164) DC21285_IO 105 arch/arm/include/asm/hardware/dec21285.h #define CSR_H_UBRLCR DC21285_IO(0x0168) DC21285_IO 106 arch/arm/include/asm/hardware/dec21285.h #define CSR_M_UBRLCR DC21285_IO(0x016c) DC21285_IO 107 arch/arm/include/asm/hardware/dec21285.h #define CSR_L_UBRLCR DC21285_IO(0x0170) DC21285_IO 108 arch/arm/include/asm/hardware/dec21285.h #define CSR_UARTCON DC21285_IO(0x0174) DC21285_IO 109 arch/arm/include/asm/hardware/dec21285.h #define CSR_UARTFLG DC21285_IO(0x0178) DC21285_IO 110 arch/arm/include/asm/hardware/dec21285.h #define CSR_IRQ_STATUS DC21285_IO(0x0180) DC21285_IO 111 arch/arm/include/asm/hardware/dec21285.h #define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184) DC21285_IO 112 arch/arm/include/asm/hardware/dec21285.h #define CSR_IRQ_ENABLE DC21285_IO(0x0188) DC21285_IO 113 arch/arm/include/asm/hardware/dec21285.h #define CSR_IRQ_DISABLE DC21285_IO(0x018c) DC21285_IO 114 arch/arm/include/asm/hardware/dec21285.h #define CSR_IRQ_SOFT DC21285_IO(0x0190) DC21285_IO 115 arch/arm/include/asm/hardware/dec21285.h #define CSR_FIQ_STATUS DC21285_IO(0x0280) DC21285_IO 116 arch/arm/include/asm/hardware/dec21285.h #define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284) DC21285_IO 117 arch/arm/include/asm/hardware/dec21285.h #define CSR_FIQ_ENABLE DC21285_IO(0x0288) DC21285_IO 118 arch/arm/include/asm/hardware/dec21285.h #define CSR_FIQ_DISABLE DC21285_IO(0x028c) DC21285_IO 119 arch/arm/include/asm/hardware/dec21285.h #define CSR_FIQ_SOFT DC21285_IO(0x0290) DC21285_IO 120 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER1_LOAD DC21285_IO(0x0300) DC21285_IO 121 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER1_VALUE DC21285_IO(0x0304) DC21285_IO 122 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER1_CNTL DC21285_IO(0x0308) DC21285_IO 123 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER1_CLR DC21285_IO(0x030c) DC21285_IO 124 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER2_LOAD DC21285_IO(0x0320) DC21285_IO 125 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER2_VALUE DC21285_IO(0x0324) DC21285_IO 126 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER2_CNTL DC21285_IO(0x0328) DC21285_IO 127 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER2_CLR DC21285_IO(0x032c) DC21285_IO 128 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER3_LOAD DC21285_IO(0x0340) DC21285_IO 129 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER3_VALUE DC21285_IO(0x0344) DC21285_IO 130 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER3_CNTL DC21285_IO(0x0348) DC21285_IO 131 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER3_CLR DC21285_IO(0x034c) DC21285_IO 132 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER4_LOAD DC21285_IO(0x0360) DC21285_IO 133 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER4_VALUE DC21285_IO(0x0364) DC21285_IO 134 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER4_CNTL DC21285_IO(0x0368) DC21285_IO 135 arch/arm/include/asm/hardware/dec21285.h #define CSR_TIMER4_CLR DC21285_IO(0x036c)