DC21285_ARMCSR_BASE  140 arch/arm/mach-footbridge/common.c 		.pfn		= __phys_to_pfn(DC21285_ARMCSR_BASE),
DC21285_ARMCSR_BASE  310 drivers/staging/isdn/avm/c4.c 	c4_poke(card, DC21285_ARMCSR_BASE + CHAN_1_CONTROL, 0);
DC21285_ARMCSR_BASE  311 drivers/staging/isdn/avm/c4.c 	c4_poke(card, DC21285_ARMCSR_BASE + CHAN_2_CONTROL, 0);
DC21285_ARMCSR_BASE  334 drivers/staging/isdn/avm/c4.c 	c4_poke(card, DC21285_ARMCSR_BASE + CHAN_1_CONTROL, 0);
DC21285_ARMCSR_BASE  335 drivers/staging/isdn/avm/c4.c 	c4_poke(card, DC21285_ARMCSR_BASE + CHAN_2_CONTROL, 0);
DC21285_ARMCSR_BASE  343 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DBELL_SA_MASK, 0)) return 5;
DC21285_ARMCSR_BASE  344 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DBELL_PCI_MASK, 0)) return 6;
DC21285_ARMCSR_BASE  345 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + SA_CONTROL, SA_CTL_ALLRIGHT))
DC21285_ARMCSR_BASE  347 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + XBUS_CYCLE, INIT_XBUS_CYCLE))
DC21285_ARMCSR_BASE  349 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + XBUS_STROBE, INIT_XBUS_STROBE))
DC21285_ARMCSR_BASE  351 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_TIMING, 0)) return 9;
DC21285_ARMCSR_BASE  367 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_TIMING, DRAM_TIMING_DEF))
DC21285_ARMCSR_BASE  370 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_0, DRAM_AD_SZ_DEF0))
DC21285_ARMCSR_BASE  372 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_1, DRAM_AD_SZ_NULL))
DC21285_ARMCSR_BASE  374 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_2, DRAM_AD_SZ_NULL))
DC21285_ARMCSR_BASE  376 drivers/staging/isdn/avm/c4.c 	if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_3, DRAM_AD_SZ_NULL))