zynq_slcr_write    66 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
zynq_slcr_write   108 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write   109 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
zynq_slcr_write   128 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
zynq_slcr_write   130 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
zynq_slcr_write   145 arch/arm/mach-zynq/slcr.c 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);