zx_writel_mask    105 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(layer + VL_CTRL0, VL_UPDATE, VL_UPDATE);
zx_writel_mask    162 drivers/gpu/drm/zte/zx_plane.c 		zx_writel_mask(rsz + RSZ_VL_CTRL_CFG, RSZ_VL_FMT_MASK, fmt);
zx_writel_mask    246 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(layer + VL_CTRL2, VL_SCALER_BYPASS_MODE,
zx_writel_mask    252 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
zx_writel_mask    268 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, 0);
zx_writel_mask    330 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(layer + GL_CTRL0, GL_UPDATE, GL_UPDATE);
zx_writel_mask    405 drivers/gpu/drm/zte/zx_plane.c 		zx_writel_mask(layer + GL_CTRL1, GL_DATA_FMT_MASK,
zx_writel_mask    409 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(layer + GL_CTRL2, GL_GLOBAL_ALPHA_MASK,
zx_writel_mask    414 drivers/gpu/drm/zte/zx_plane.c 		zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
zx_writel_mask    417 drivers/gpu/drm/zte/zx_plane.c 		zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
zx_writel_mask    419 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, CSC_WORK_ENABLE);
zx_writel_mask    422 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(layer + GL_CTRL3, GL_SCALER_BYPASS_MODE,
zx_writel_mask    428 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
zx_writel_mask    230 drivers/gpu/drm/zte/zx_vga.c 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_COMBO, VGA_CMD_COMBO);
zx_writel_mask    231 drivers/gpu/drm/zte/zx_vga.c 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_RW, 0);
zx_writel_mask    237 drivers/gpu/drm/zte/zx_vga.c 		zx_writel_mask(vga->mmio + VGA_RXF_CTRL, VGA_RX_FIFO_CLEAR,
zx_writel_mask    244 drivers/gpu/drm/zte/zx_vga.c 		zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS,
zx_writel_mask    370 drivers/gpu/drm/zte/zx_vga.c 	zx_writel_mask(vga->mmio + VGA_I2C_STATUS, VGA_CLEAR_IRQ,
zx_writel_mask    420 drivers/gpu/drm/zte/zx_vga.c 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS, VGA_CMD_TRANS);
zx_writel_mask    229 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);
zx_writel_mask    244 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
zx_writel_mask    246 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
zx_writel_mask    250 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
zx_writel_mask    253 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
zx_writel_mask    254 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
zx_writel_mask    258 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
zx_writel_mask    262 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,
zx_writel_mask    266 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
zx_writel_mask    270 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
zx_writel_mask    274 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);
zx_writel_mask    283 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);
zx_writel_mask    286 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
zx_writel_mask    298 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);
zx_writel_mask    338 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + reg, 0x7 << shift,
zx_writel_mask    343 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,
zx_writel_mask    409 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
zx_writel_mask    421 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask,
zx_writel_mask    425 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
zx_writel_mask    429 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,
zx_writel_mask    431 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
zx_writel_mask    435 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_INTERLACE_BUF_CTRL, CHN_INTERLACE_EN,
zx_writel_mask    442 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);
zx_writel_mask    469 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);
zx_writel_mask    472 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
zx_writel_mask    505 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,
zx_writel_mask    516 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->timing + TIMING_INT_CTRL,
zx_writel_mask    617 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);
zx_writel_mask    618 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
zx_writel_mask    620 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,
zx_writel_mask    622 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
zx_writel_mask    626 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);
zx_writel_mask    637 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);
zx_writel_mask    716 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,
zx_writel_mask    720 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,
zx_writel_mask    724 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,
zx_writel_mask    726 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,
zx_writel_mask    757 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);