zx_writel 31 drivers/gpu/drm/zte/zx_drm_drv.h zx_writel(reg, tmp); zx_writel 110 drivers/gpu/drm/zte/zx_plane.c zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1); zx_writel 156 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); zx_writel 157 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); zx_writel 173 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); zx_writel 174 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); zx_writel 175 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w)); zx_writel 176 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h)); zx_writel 222 drivers/gpu/drm/zte/zx_plane.c zx_writel(paddr_reg, paddr); zx_writel 227 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); zx_writel 230 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y)); zx_writel 233 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_POS_END, zx_writel 237 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_STRIDE, LUMA_STRIDE(fb->pitches[0]) | zx_writel 243 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_CTRL1, fmt); zx_writel 335 drivers/gpu/drm/zte/zx_plane.c zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1); zx_writel 343 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); zx_writel 344 drivers/gpu/drm/zte/zx_plane.c zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); zx_writel 387 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_ADDR, paddr); zx_writel 390 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); zx_writel 393 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y)); zx_writel 396 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_POS_END, zx_writel 400 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_STRIDE, stride & 0xffff); zx_writel 485 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_SATURATION, 0x200); zx_writel 486 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_HUE, 0x0); zx_writel 487 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_BRIGHT, 0x0); zx_writel 488 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_CONTRAST, 0x200); zx_writel 490 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_THRESHOLD_COL1, (0x3ac << 16) | 0x40); zx_writel 491 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_THRESHOLD_COL2, (0x3c0 << 16) | 0x40); zx_writel 492 drivers/gpu/drm/zte/zx_plane.c zx_writel(hbsc + HBSC_THRESHOLD_COL3, (0x3c0 << 16) | 0x40); zx_writel 167 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_VIDEO_INFO, zmode->video_info); zx_writel 168 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_VIDEO_RES, zmode->video_res); zx_writel 169 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_FIELD1_PARAM, zmode->field1_param); zx_writel 170 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_FIELD2_PARAM, zmode->field2_param); zx_writel 171 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_LINE_O_1, zmode->burst_line_odd1); zx_writel 172 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_LINE_E_1, zmode->burst_line_even1); zx_writel 173 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_LINE_O_2, zmode->burst_line_odd2); zx_writel 174 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_LINE_E_2, zmode->burst_line_even2); zx_writel 175 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_LINE_TIMING_PARAM, zx_writel 177 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_WEIGHT_VALUE, zmode->weight_value); zx_writel 178 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_BLANK_BLACK_LEVEL, zx_writel 180 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_BURST_LEVEL, zmode->burst_level); zx_writel 181 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_CONTROL_PARAM, zmode->control_param); zx_writel 182 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_SUB_CARRIER_PHASE1, zx_writel 184 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_PHASE_LINE_INCR_CVBS, zx_writel 199 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_ENABLE, 1); zx_writel 207 drivers/gpu/drm/zte/zx_tvenc.c zx_writel(tvenc->mmio + VENC_ENABLE, 0); zx_writel 89 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0); zx_writel 99 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, zx_writel 109 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_HAS_DEVICE); zx_writel 241 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_SUB_ADDR, offset); zx_writel 278 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_DEVICE_ADDR, msg->addr); zx_writel 385 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, zx_writel 409 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_CLK_DIV_FS, div); zx_writel 412 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_PARA, 0x80); zx_writel 413 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_NO_DEVICE); zx_writel 419 drivers/gpu/drm/zte/zx_vga.c zx_writel(vga->mmio + VGA_DEVICE_ADDR, DDC_ADDR); zx_writel 349 drivers/gpu/drm/zte/zx_vou.c zx_writel(zcrtc->chnreg + CHN_UPDATE, 1); zx_writel 372 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_active, val); zx_writel 377 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_htiming, val); zx_writel 382 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_vtiming, val); zx_writel 391 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + SEC_V_ACTIVE, val); zx_writel 400 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->sec_vtiming, val); zx_writel 416 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_shift, val); zx_writel 417 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL); zx_writel 689 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, state); zx_writel 699 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_CLRSTA, state); zx_writel 730 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) | zx_writel 737 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->vouctl + VOU_SOFT_RST, ~0); zx_writel 740 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->vouctl + VOU_CLK_EN, ~0); zx_writel 743 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_CLRSTA, ~0); zx_writel 744 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, ~0); zx_writel 747 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE); zx_writel 748 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE); zx_writel 751 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);