xgene_set_bits    139 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PHY_CONTROL_SET(dst, val)	xgene_set_bits(dst, val, 0, 16)
xgene_set_bits    157 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_TXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 29, 3)
xgene_set_bits    158 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)
xgene_set_bits    160 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)
xgene_set_bits    161 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)
xgene_set_bits    162 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)
xgene_set_bits    163 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)
xgene_set_bits    164 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_NXTFPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 20, 4)
xgene_set_bits    165 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)
xgene_set_bits    166 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_WAITASYNCRD_SET(dst, val)		xgene_set_bits(dst, val, 0, 16)
xgene_set_bits    205 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PHY_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 8, 5)
xgene_set_bits    206 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define REG_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 0, 5)
xgene_set_bits    207 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define ENET_INTERFACE_MODE2_SET(dst, val)	xgene_set_bits(dst, val, 8, 2)
xgene_set_bits    208 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define MGMT_CLOCK_SEL_SET(dst, val)		xgene_set_bits(dst, val, 0, 3)
xgene_set_bits     58 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define RSIF_CLE_BUFF_THRESH_SET(dst, val)     xgene_set_bits(dst, val, 0, 3)
xgene_set_bits     61 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)