wrmsrl_safe       252 arch/x86/events/core.c 	ret = wrmsrl_safe(reg, val);
wrmsrl_safe      2306 arch/x86/events/intel/core.c 		wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
wrmsrl_safe      2307 arch/x86/events/intel/core.c 		wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
wrmsrl_safe      2310 arch/x86/events/intel/core.c 		wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
wrmsrl_safe      4097 arch/x86/events/intel/core.c 	if (wrmsrl_safe(msr, val_tmp) ||
wrmsrl_safe       185 arch/x86/events/intel/knc.c 	(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
wrmsrl_safe       196 arch/x86/events/intel/knc.c 	(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
wrmsrl_safe       912 arch/x86/events/intel/p4.c 	(void)wrmsrl_safe(hwc->config_base,
wrmsrl_safe       945 arch/x86/events/intel/p4.c 	(void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE,	(u64)bind->metric_pebs);
wrmsrl_safe       946 arch/x86/events/intel/p4.c 	(void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT,	(u64)bind->metric_vert);
wrmsrl_safe       980 arch/x86/events/intel/p4.c 	(void)wrmsrl_safe(escr_addr, escr_conf);
wrmsrl_safe       981 arch/x86/events/intel/p4.c 	(void)wrmsrl_safe(hwc->config_base,
wrmsrl_safe      1372 arch/x86/events/intel/p4.c 		wrmsrl_safe(reg, 0ULL);
wrmsrl_safe       164 arch/x86/events/intel/p6.c 	(void)wrmsrl_safe(hwc->config_base, val);
wrmsrl_safe       181 arch/x86/events/intel/p6.c 	(void)wrmsrl_safe(hwc->config_base, val);
wrmsrl_safe       397 arch/x86/include/asm/msr.h 	return wrmsrl_safe(msr_no, q);
wrmsrl_safe       878 arch/x86/kernel/cpu/amd.c 			wrmsrl_safe(MSR_F15H_IC_CFG, value);
wrmsrl_safe      1722 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
wrmsrl_safe      1723 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
wrmsrl_safe      1725 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
wrmsrl_safe      1728 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
wrmsrl_safe      1729 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
wrmsrl_safe      1730 arch/x86/kernel/cpu/common.c 	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
wrmsrl_safe       498 arch/x86/kernel/cpu/mce/intel.c 			wrmsrl_safe(MSR_PPIN_CTL,  val | 2UL);
wrmsrl_safe       358 arch/x86/kernel/cpu/mce/therm_throt.c 		wrmsrl_safe(MSR_HWP_STATUS, 0);
wrmsrl_safe       308 arch/x86/kvm/x86.c 	err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
wrmsrl_safe        59 arch/x86/lib/msr.c 	return wrmsrl_safe(msr, m->q);
wrmsrl_safe       203 drivers/platform/x86/intel_speed_select_if/isst_if_common.c 				wrmsrl_safe(sst_cmd->cmd, sst_cmd->data);
wrmsrl_safe        44 drivers/platform/x86/intel_turbo_max_3.c 	ret = wrmsrl_safe(MSR_OC_MAILBOX, value);
wrmsrl_safe       112 drivers/powercap/intel_rapl_msr.c 	ra->err = wrmsrl_safe(msr, val);
wrmsrl_safe       172 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c 	err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val);