wrmsrl 366 arch/x86/events/amd/ibs.c wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask); wrmsrl 381 arch/x86/events/amd/ibs.c wrmsrl(hwc->config_base, config); wrmsrl 383 arch/x86/events/amd/ibs.c wrmsrl(hwc->config_base, config); wrmsrl 106 arch/x86/events/amd/uncore.c wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); wrmsrl 109 arch/x86/events/amd/uncore.c wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); wrmsrl 117 arch/x86/events/amd/uncore.c wrmsrl(hwc->config_base, hwc->config); wrmsrl 628 arch/x86/events/core.c wrmsrl(x86_pmu_config_addr(idx), val); wrmsrl 1237 arch/x86/events/core.c wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); wrmsrl 1245 arch/x86/events/core.c wrmsrl(hwc->event_base, wrmsrl 1953 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); wrmsrl 1973 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, wrmsrl 2047 arch/x86/events/intel/core.c wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); wrmsrl 2048 arch/x86/events/intel/core.c wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); wrmsrl 2051 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); wrmsrl 2052 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); wrmsrl 2062 arch/x86/events/intel/core.c wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); wrmsrl 2079 arch/x86/events/intel/core.c wrmsrl(MSR_TSX_FORCE_ABORT, val); wrmsrl 2129 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); wrmsrl 2141 arch/x86/events/intel/core.c wrmsrl(hwc->config_base, ctrl_val); wrmsrl 2228 arch/x86/events/intel/core.c wrmsrl(hwc->config_base, ctrl_val); wrmsrl 2286 arch/x86/events/intel/core.c wrmsrl(event->hw.event_base, 0); wrmsrl 2318 arch/x86/events/intel/core.c wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); wrmsrl 4114 arch/x86/events/intel/core.c wrmsrl(msr, val_old); wrmsrl 1099 arch/x86/events/intel/ds.c wrmsrl(MSR_RELOAD_PMC0 + hwc->idx, ds->pebs_event_reset[hwc->idx]); wrmsrl 1120 arch/x86/events/intel/ds.c wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg); wrmsrl 1178 arch/x86/events/intel/ds.c wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); wrmsrl 1188 arch/x86/events/intel/ds.c wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); wrmsrl 1196 arch/x86/events/intel/ds.c wrmsrl(MSR_IA32_PEBS_ENABLE, 0); wrmsrl 2101 arch/x86/events/intel/ds.c wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); wrmsrl 164 arch/x86/events/intel/knc.c wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); wrmsrl 173 arch/x86/events/intel/knc.c wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); wrmsrl 210 arch/x86/events/intel/knc.c wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); wrmsrl 172 arch/x86/events/intel/lbr.c wrmsrl(MSR_LBR_SELECT, lbr_select); wrmsrl 185 arch/x86/events/intel/lbr.c wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); wrmsrl 194 arch/x86/events/intel/lbr.c wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); wrmsrl 202 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + i, 0); wrmsrl 210 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + i, 0); wrmsrl 211 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_to + i, 0); wrmsrl 213 arch/x86/events/intel/lbr.c wrmsrl(MSR_LBR_INFO_0 + i, 0); wrmsrl 314 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + idx, val); wrmsrl 319 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_to + idx, val); wrmsrl 373 arch/x86/events/intel/lbr.c wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); wrmsrl 381 arch/x86/events/intel/lbr.c wrmsrl(MSR_LBR_INFO_0 + lbr_idx, 0); wrmsrl 384 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_tos, tos); wrmsrl 862 arch/x86/events/intel/p4.c wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); wrmsrl 145 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); wrmsrl 155 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); wrmsrl 454 arch/x86/events/intel/pt.c wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a); wrmsrl 459 arch/x86/events/intel/pt.c wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b); wrmsrl 477 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_STATUS, 0); wrmsrl 507 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_CTL, reg); wrmsrl 521 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_CTL, ctl); wrmsrl 541 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf)); wrmsrl 545 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); wrmsrl 895 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_STATUS, status); wrmsrl 1418 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config); wrmsrl 202 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); wrmsrl 207 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); wrmsrl 221 arch/x86/events/intel/uncore_nhmex.c wrmsrl(msr, config); wrmsrl 236 arch/x86/events/intel/uncore_nhmex.c wrmsrl(msr, config); wrmsrl 242 arch/x86/events/intel/uncore_nhmex.c wrmsrl(event->hw.config_base, 0); wrmsrl 250 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); wrmsrl 252 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); wrmsrl 254 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); wrmsrl 384 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, reg1->config); wrmsrl 385 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg2->config); wrmsrl 387 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | wrmsrl 469 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, 0); wrmsrl 470 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg1->config); wrmsrl 471 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 2, reg2->config); wrmsrl 472 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); wrmsrl 474 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); wrmsrl 844 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 0, 16), wrmsrl 848 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 1, 16), wrmsrl 852 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, 0); wrmsrl 854 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 1, wrmsrl 856 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK & wrmsrl 858 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN); wrmsrl 862 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); wrmsrl 1123 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); wrmsrl 1126 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); wrmsrl 1130 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port), wrmsrl 1134 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port), wrmsrl 1136 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); wrmsrl 1137 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config); wrmsrl 1140 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port), wrmsrl 1142 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); wrmsrl 1143 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); wrmsrl 1147 arch/x86/events/intel/uncore_nhmex.c wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | wrmsrl 126 arch/x86/events/intel/uncore_snb.c wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); wrmsrl 128 arch/x86/events/intel/uncore_snb.c wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); wrmsrl 133 arch/x86/events/intel/uncore_snb.c wrmsrl(event->hw.config_base, 0); wrmsrl 139 arch/x86/events/intel/uncore_snb.c wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, wrmsrl 146 arch/x86/events/intel/uncore_snb.c wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, wrmsrl 153 arch/x86/events/intel/uncore_snb.c wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); wrmsrl 238 arch/x86/events/intel/uncore_snb.c wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, wrmsrl 249 arch/x86/events/intel/uncore_snb.c wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, wrmsrl 256 arch/x86/events/intel/uncore_snb.c wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); wrmsrl 925 arch/x86/events/intel/uncore_snb.c wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); wrmsrl 930 arch/x86/events/intel/uncore_snb.c wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); wrmsrl 938 arch/x86/events/intel/uncore_snb.c wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); wrmsrl 940 arch/x86/events/intel/uncore_snb.c wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); wrmsrl 532 arch/x86/events/intel/uncore_snbep.c wrmsrl(msr, config); wrmsrl 545 arch/x86/events/intel/uncore_snbep.c wrmsrl(msr, config); wrmsrl 555 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); wrmsrl 557 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); wrmsrl 565 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config); wrmsrl 573 arch/x86/events/intel/uncore_snbep.c wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); wrmsrl 1387 arch/x86/events/intel/uncore_snbep.c wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); wrmsrl 1638 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); wrmsrl 1639 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 6, filter >> 32); wrmsrl 1642 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); wrmsrl 2622 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); wrmsrl 2623 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 1, filter >> 32); wrmsrl 2626 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); wrmsrl 2671 arch/x86/events/intel/uncore_snbep.c wrmsrl(msr, flags); wrmsrl 3566 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); wrmsrl 4086 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, reg1->config); wrmsrl 4088 arch/x86/events/intel/uncore_snbep.c wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); wrmsrl 841 arch/x86/events/perf_event.h wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); wrmsrl 842 arch/x86/events/perf_event.h wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); wrmsrl 857 arch/x86/events/perf_event.h wrmsrl(hwc->config_base, hwc->config); wrmsrl 53 arch/x86/hyperv/hv_apic.c wrmsrl(HV_X64_MSR_ICR, reg_val); wrmsrl 97 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, val); wrmsrl 124 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); wrmsrl 172 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); wrmsrl 173 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); wrmsrl 186 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); wrmsrl 208 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, 0); wrmsrl 219 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); wrmsrl 302 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); wrmsrl 306 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); wrmsrl 313 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); wrmsrl 339 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); wrmsrl 350 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); wrmsrl 354 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64); wrmsrl 377 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P0, err); wrmsrl 378 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P1, guest_id); wrmsrl 379 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P2, regs->ip); wrmsrl 380 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P3, regs->ax); wrmsrl 381 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P4, regs->sp); wrmsrl 386 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_CRASH_NOTIFY); wrmsrl 402 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P0, 0); wrmsrl 403 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P1, 0); wrmsrl 404 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P2, 0); wrmsrl 405 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P3, pa); wrmsrl 406 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_P4, size); wrmsrl 412 arch/x86/hyperv/hv_init.c wrmsrl(HV_X64_MSR_CRASH_CTL, wrmsrl 249 arch/x86/include/asm/apic.h wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); wrmsrl 44 arch/x86/include/asm/fsgsbase.h wrmsrl(MSR_FS_BASE, fsbase); wrmsrl 49 arch/x86/include/asm/fsgsbase.h wrmsrl(MSR_KERNEL_GS_BASE, gsbase); wrmsrl 16 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick) wrmsrl 18 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val) wrmsrl 21 arch/x86/include/asm/mshyperv.h #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val) wrmsrl 24 arch/x86/include/asm/mshyperv.h #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val) wrmsrl 27 arch/x86/include/asm/mshyperv.h #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val) wrmsrl 31 arch/x86/include/asm/mshyperv.h #define hv_signal_eom() wrmsrl(HV_X64_MSR_EOM, 0) wrmsrl 36 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_SINT0 + int_num, val) wrmsrl 47 arch/x86/include/asm/mshyperv.h wrmsrl(HV_X64_MSR_REFERENCE_TSC, val) wrmsrl 369 arch/x86/include/asm/msr.h wrmsrl(msr_no, q); wrmsrl 765 arch/x86/include/asm/processor.h wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); wrmsrl 114 arch/x86/include/asm/virtext.h wrmsrl(MSR_VM_HSAVE_PA, 0); wrmsrl 116 arch/x86/include/asm/virtext.h wrmsrl(MSR_EFER, efer & ~EFER_SVME); wrmsrl 476 arch/x86/kernel/apic/apic.c wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); wrmsrl 1805 arch/x86/kernel/apic/apic.c wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); wrmsrl 1806 arch/x86/kernel/apic/apic.c wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); wrmsrl 1817 arch/x86/kernel/apic/apic.c wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); wrmsrl 181 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_SPEC_CTRL, msrval); wrmsrl 222 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); wrmsrl 224 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_AMD64_LS_CFG, msrval); wrmsrl 445 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); wrmsrl 881 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); wrmsrl 957 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); wrmsrl 1181 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); wrmsrl 1385 arch/x86/kernel/cpu/bugs.c wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); wrmsrl 577 arch/x86/kernel/cpu/common.c wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); wrmsrl 1359 arch/x86/kernel/cpu/common.c wrmsrl(MSR_FS_BASE, 1); wrmsrl 1364 arch/x86/kernel/cpu/common.c wrmsrl(MSR_FS_BASE, old_base); wrmsrl 1712 arch/x86/kernel/cpu/common.c wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); wrmsrl 1715 arch/x86/kernel/cpu/common.c wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); wrmsrl 1727 arch/x86/kernel/cpu/common.c wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); wrmsrl 1734 arch/x86/kernel/cpu/common.c wrmsrl(MSR_SYSCALL_MASK, wrmsrl 1894 arch/x86/kernel/cpu/common.c wrmsrl(MSR_FS_BASE, 0); wrmsrl 1895 arch/x86/kernel/cpu/common.c wrmsrl(MSR_KERNEL_GS_BASE, 0); wrmsrl 652 arch/x86/kernel/cpu/intel.c wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); wrmsrl 97 arch/x86/kernel/cpu/intel_epb.c wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); wrmsrl 614 arch/x86/kernel/cpu/mce/amd.c wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); wrmsrl 622 arch/x86/kernel/cpu/mce/amd.c wrmsrl(MSR_K7_HWCR, hwcr); wrmsrl 935 arch/x86/kernel/cpu/mce/amd.c wrmsrl(msr_stat, 0); wrmsrl 961 arch/x86/kernel/cpu/mce/amd.c wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); wrmsrl 426 arch/x86/kernel/cpu/mce/core.c wrmsrl(msr, v); wrmsrl 1572 arch/x86/kernel/cpu/mce/core.c wrmsrl(msr_ops.ctl(i), b->ctl); wrmsrl 1573 arch/x86/kernel/cpu/mce/core.c wrmsrl(msr_ops.status(i), 0); wrmsrl 2016 arch/x86/kernel/cpu/mce/core.c wrmsrl(msr_ops.ctl(i), 0); wrmsrl 2365 arch/x86/kernel/cpu/mce/core.c wrmsrl(msr_ops.ctl(i), b->ctl); wrmsrl 462 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); wrmsrl 466 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); wrmsrl 467 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); wrmsrl 469 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); wrmsrl 470 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); wrmsrl 473 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); wrmsrl 474 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); wrmsrl 476 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); wrmsrl 477 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); wrmsrl 478 arch/x86/kernel/cpu/mce/inject.c wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); wrmsrl 168 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); wrmsrl 306 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(i), val); wrmsrl 361 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); wrmsrl 455 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); wrmsrl 467 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCG_EXT_CTL, val); wrmsrl 829 arch/x86/kernel/cpu/microcode/intel.c wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); wrmsrl 368 arch/x86/kernel/cpu/resctrl/core.c wrmsrl(r->msr_base + i, d->ctrl_val[i]); wrmsrl 393 arch/x86/kernel/cpu/resctrl/core.c wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r)); wrmsrl 402 arch/x86/kernel/cpu/resctrl/core.c wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]); wrmsrl 416 arch/x86/kernel/cpu/resctrl/monitor.c wrmsrl(cur_msr, delay_bw_map(new_msr_val, r_mba)); wrmsrl 1721 arch/x86/kernel/cpu/resctrl/rdtgroup.c wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); wrmsrl 1728 arch/x86/kernel/cpu/resctrl/rdtgroup.c wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); wrmsrl 36 arch/x86/kernel/cpu/tsx.c wrmsrl(MSR_IA32_TSX_CTRL, tsx); wrmsrl 55 arch/x86/kernel/cpu/tsx.c wrmsrl(MSR_IA32_TSX_CTRL, tsx); wrmsrl 288 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); wrmsrl 322 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); wrmsrl 335 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_PV_EOI_EN, pa); wrmsrl 347 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); wrmsrl 362 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_PV_EOI_EN, 0); wrmsrl 554 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_PV_EOI_EN, 0); wrmsrl 864 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_POLL_CONTROL, 0); wrmsrl 869 arch/x86/kernel/kvm.c wrmsrl(MSR_KVM_POLL_CONTROL, 1); wrmsrl 74 arch/x86/kernel/kvmclock.c wrmsrl(msr_kvm_wall_clock, slow_virt_to_phys(&wall_clock)); wrmsrl 180 arch/x86/kernel/kvmclock.c wrmsrl(msr_kvm_system_time, pa); wrmsrl 214 arch/x86/kernel/mmconf-fam10h_64.c wrmsrl(address, val); wrmsrl 203 arch/x86/kernel/process.c wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); wrmsrl 367 arch/x86/kernel/process.c wrmsrl(MSR_AMD64_LS_CFG, msr); wrmsrl 384 arch/x86/kernel/process.c wrmsrl(MSR_AMD64_LS_CFG, msr); wrmsrl 394 arch/x86/kernel/process.c wrmsrl(MSR_AMD64_LS_CFG, msr); wrmsrl 403 arch/x86/kernel/process.c wrmsrl(MSR_AMD64_LS_CFG, msr); wrmsrl 413 arch/x86/kernel/process.c wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); wrmsrl 452 arch/x86/kernel/process.c wrmsrl(MSR_IA32_SPEC_CTRL, msr); wrmsrl 512 arch/x86/kernel/process.c wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); wrmsrl 268 arch/x86/kernel/process_64.c wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE, wrmsrl 30 arch/x86/kernel/reboot_fixups_32.c wrmsrl(MSR_DIVIL_SOFT_RESET, 1ULL); wrmsrl 71 arch/x86/kernel/tsc_sync.c wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); wrmsrl 103 arch/x86/kernel/tsc_sync.c wrmsrl(MSR_IA32_TSC_ADJUST, 0); wrmsrl 192 arch/x86/kernel/tsc_sync.c wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); wrmsrl 489 arch/x86/kernel/tsc_sync.c wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); wrmsrl 902 arch/x86/kvm/svm.c wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); wrmsrl 939 arch/x86/kvm/svm.c wrmsrl(MSR_EFER, efer | EFER_SVME); wrmsrl 941 arch/x86/kvm/svm.c wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); wrmsrl 944 arch/x86/kvm/svm.c wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); wrmsrl 2337 arch/x86/kvm/svm.c wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); wrmsrl 2342 arch/x86/kvm/svm.c wrmsrl(MSR_TSC_AUX, svm->tsc_aux); wrmsrl 2362 arch/x86/kvm/svm.c wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); wrmsrl 2370 arch/x86/kvm/svm.c wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); wrmsrl 4355 arch/x86/kvm/svm.c wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); wrmsrl 4408 arch/x86/kvm/svm.c wrmsrl(MSR_TSC_AUX, svm->tsc_aux); wrmsrl 5202 arch/x86/kvm/svm.c wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid)); wrmsrl 5798 arch/x86/kvm/svm.c wrmsrl(MSR_GS_BASE, svm->host.gs_base); wrmsrl 913 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_PEBS_ENABLE, 0); wrmsrl 1025 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); wrmsrl 1026 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); wrmsrl 1027 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); wrmsrl 1028 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); wrmsrl 1030 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); wrmsrl 1031 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); wrmsrl 1060 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_CTL, 0); wrmsrl 1077 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); wrmsrl 1162 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); wrmsrl 1206 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); wrmsrl 1227 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_KERNEL_GS_BASE, data); wrmsrl 2000 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); wrmsrl 2249 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); wrmsrl 5989 arch/x86/kvm/vmx/vmx.c wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); wrmsrl 259 arch/x86/kvm/x86.c wrmsrl(shared_msrs_global.msrs[slot], values->host); wrmsrl 228 arch/x86/mm/pat.c wrmsrl(MSR_IA32_CR_PAT, pat); wrmsrl 244 arch/x86/mm/pat.c wrmsrl(MSR_IA32_CR_PAT, pat); wrmsrl 222 arch/x86/oprofile/nmi_int.c wrmsrl(counters[i].addr, multiplex[virt].saved); wrmsrl 364 arch/x86/oprofile/nmi_int.c wrmsrl(controls[i].addr, controls[i].saved); wrmsrl 369 arch/x86/oprofile/nmi_int.c wrmsrl(counters[i].addr, counters[i].saved); wrmsrl 156 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); wrmsrl 185 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSOPCTL, ctl); wrmsrl 211 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSFETCHCTL, val); wrmsrl 248 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSOPCTL, val); wrmsrl 259 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); wrmsrl 263 arch/x86/oprofile/op_model_amd.c wrmsrl(MSR_AMD64_IBSOPCTL, 0); wrmsrl 282 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 356 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 361 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->counters[i].addr, -1LL); wrmsrl 371 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); wrmsrl 377 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 396 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); wrmsrl 415 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 435 arch/x86/oprofile/op_model_amd.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 606 arch/x86/oprofile/op_model_p4.c wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address, wrmsrl 651 arch/x86/oprofile/op_model_p4.c wrmsrl(p4_counters[real].counter_address, wrmsrl 655 arch/x86/oprofile/op_model_p4.c wrmsrl(p4_counters[real].counter_address, wrmsrl 103 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 108 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->counters[i].addr, -1LL); wrmsrl 115 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->counters[i].addr, -reset_value[i]); wrmsrl 119 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 140 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->counters[i].addr, -reset_value[i]); wrmsrl 167 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 183 arch/x86/oprofile/op_model_ppro.c wrmsrl(msrs->controls[i].addr, val); wrmsrl 339 arch/x86/pci/amd_bus.c wrmsrl(MSR_AMD64_NB_CFG, reg); wrmsrl 330 arch/x86/platform/olpc/olpc-xo1-sci.c wrmsrl(0x51400020, lo); wrmsrl 55 arch/x86/power/cpu.c wrmsrl(msr->info.msr_no, msr->info.reg.q); wrmsrl 197 arch/x86/power/cpu.c wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); wrmsrl 207 arch/x86/power/cpu.c wrmsrl(MSR_EFER, ctxt->efer); wrmsrl 230 arch/x86/power/cpu.c wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); wrmsrl 254 arch/x86/power/cpu.c wrmsrl(MSR_FS_BASE, ctxt->fs_base); wrmsrl 255 arch/x86/power/cpu.c wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); wrmsrl 44 arch/x86/xen/suspend.c wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); wrmsrl 62 arch/x86/xen/suspend.c wrmsrl(MSR_IA32_SPEC_CTRL, 0); wrmsrl 117 drivers/cpufreq/acpi-cpufreq.c wrmsrl(msr_addr, val); wrmsrl 232 drivers/cpufreq/e_powersaver.c wrmsrl(MSR_IA32_MISC_ENABLE, val); wrmsrl 1637 drivers/cpufreq/intel_pstate.c wrmsrl(MSR_HWP_REQUEST, hwp_req); wrmsrl 1650 drivers/cpufreq/intel_pstate.c wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); wrmsrl 1806 drivers/cpufreq/intel_pstate.c wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); wrmsrl 147 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_BCR2, bcr2.val); wrmsrl 156 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_BCR2, bcr2.val); wrmsrl 183 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 197 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 202 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 215 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 220 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 234 drivers/cpufreq/longhaul.c wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); wrmsrl 228 drivers/cpufreq/powernow-k7.c wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); wrmsrl 243 drivers/cpufreq/powernow-k7.c wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); wrmsrl 961 drivers/idle/intel_idle.c wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); wrmsrl 969 drivers/idle/intel_idle.c wrmsrl(MSR_IA32_POWER_CTL, msr_bits); wrmsrl 1377 drivers/idle/intel_idle.c wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); wrmsrl 1378 drivers/idle/intel_idle.c wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); wrmsrl 384 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); wrmsrl 389 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); wrmsrl 419 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); wrmsrl 424 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); wrmsrl 442 drivers/platform/x86/intel_ips.c wrmsrl(IA32_PERF_CTL, perf_ctl); wrmsrl 480 drivers/platform/x86/intel_ips.c wrmsrl(IA32_PERF_CTL, perf_ctl); wrmsrl 1617 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); wrmsrl 1618 drivers/platform/x86/intel_ips.c wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); wrmsrl 57 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c wrmsrl(MSR_OS_MAILBOX_DATA, command_data); wrmsrl 64 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c wrmsrl(MSR_OS_MAILBOX_INTERFACE, data); wrmsrl 283 drivers/thermal/intel/x86_pkg_temp_thermal.c wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, wr_val); wrmsrl 374 drivers/video/fbdev/geode/lxfb_ops.c wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); wrmsrl 430 drivers/video/fbdev/geode/lxfb_ops.c wrmsrl(MSR_LX_SPARE_MSR, msrval); wrmsrl 669 drivers/video/fbdev/geode/lxfb_ops.c wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); wrmsrl 733 drivers/video/fbdev/geode/lxfb_ops.c wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); wrmsrl 734 drivers/video/fbdev/geode/lxfb_ops.c wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); wrmsrl 138 drivers/video/fbdev/geode/suspend_gx.c wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); wrmsrl 154 drivers/video/fbdev/geode/video_gx.c wrmsrl(MSR_GLCP_DOTPLL, dotpll); wrmsrl 162 drivers/video/fbdev/geode/video_gx.c wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); wrmsrl 166 drivers/video/fbdev/geode/video_gx.c wrmsrl(MSR_GLCP_DOTPLL, dotpll); wrmsrl 186 drivers/video/fbdev/geode/video_gx.c wrmsrl(MSR_GX_MSR_PADSEL, val);