writel_bits_relaxed 132 drivers/gpu/drm/meson/meson_crtc.c writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, writel_bits_relaxed 180 drivers/gpu/drm/meson/meson_crtc.c writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND | writel_bits_relaxed 235 drivers/gpu/drm/meson/meson_crtc.c writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, writel_bits_relaxed 253 drivers/gpu/drm/meson/meson_crtc.c writel_bits_relaxed(3 << 8, 3 << 8, writel_bits_relaxed 259 drivers/gpu/drm/meson/meson_crtc.c writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | writel_bits_relaxed 494 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0x3, 0, writel_bits_relaxed 496 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0xf << 8, 0, writel_bits_relaxed 506 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), writel_bits_relaxed 511 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, writel_bits_relaxed 514 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, writel_bits_relaxed 689 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(0x3, 0, writel_bits_relaxed 941 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(BIT(15), BIT(15), writel_bits_relaxed 943 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(BIT(15), BIT(15), writel_bits_relaxed 522 drivers/gpu/drm/meson/meson_overlay.c writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, writel_bits_relaxed 147 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, writel_bits_relaxed 154 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, writel_bits_relaxed 161 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(OSD_REPLACE_EN, 0, writel_bits_relaxed 168 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(OSD_REPLACE_EN, 0, writel_bits_relaxed 331 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, writel_bits_relaxed 334 drivers/gpu/drm/meson/meson_plane.c writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, writel_bits_relaxed 1041 drivers/gpu/drm/meson/meson_venc.c writel_bits_relaxed(0xff, 0xff, writel_bits_relaxed 1396 drivers/gpu/drm/meson/meson_venc.c writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH, writel_bits_relaxed 1777 drivers/gpu/drm/meson/meson_venc.c writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | writel_bits_relaxed 187 drivers/gpu/drm/meson/meson_venc_cvbs.c writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, writel_bits_relaxed 102 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, writel_bits_relaxed 146 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(3 << 30, m[21] << 30, writel_bits_relaxed 148 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(7 << 16, m[22] << 16, writel_bits_relaxed 152 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, writel_bits_relaxed 154 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(1), 0, writel_bits_relaxed 165 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, writel_bits_relaxed 167 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, writel_bits_relaxed 218 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(0x7 << 29, 7 << 29, writel_bits_relaxed 221 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(0x7 << 29, 0, writel_bits_relaxed 245 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(7 << 27, 7 << 27, writel_bits_relaxed 248 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(7 << 27, 0, writel_bits_relaxed 251 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(31), BIT(31), writel_bits_relaxed 323 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(VIU_SW_RESET_OSD1, VIU_SW_RESET_OSD1, writel_bits_relaxed 325 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(VIU_SW_RESET_OSD1, 0, writel_bits_relaxed 350 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0, writel_bits_relaxed 352 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0, writel_bits_relaxed 379 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, writel_bits_relaxed 382 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, writel_bits_relaxed 388 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0, writel_bits_relaxed 421 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc), writel_bits_relaxed 97 drivers/gpu/drm/meson/meson_vpp.c writel_bits_relaxed(0xff << 16, 0xff << 16, writel_bits_relaxed 111 drivers/gpu/drm/meson/meson_vpp.c writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, writel_bits_relaxed 118 drivers/gpu/drm/meson/meson_vpp.c writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, writel_bits_relaxed 122 drivers/gpu/drm/meson/meson_vpp.c writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, writel_bits_relaxed 126 drivers/gpu/drm/meson/meson_vpp.c writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | writel_bits_relaxed 309 drivers/media/platform/meson/ao-cec.c writel_bits_relaxed(cfg, enable ? cfg : 0, writel_bits_relaxed 550 drivers/media/platform/meson/ao-cec.c writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET, writel_bits_relaxed 557 drivers/media/platform/meson/ao-cec.c writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK, writel_bits_relaxed 565 drivers/media/platform/meson/ao-cec.c writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0, writel_bits_relaxed 230 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, writel_bits_relaxed 288 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_XCH, SPICC_XCH, writel_bits_relaxed 388 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); writel_bits_relaxed 448 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); writel_bits_relaxed 461 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);