write_csr 1117 drivers/firewire/core-transaction.c card->driver->write_csr(card, reg, be32_to_cpu(*data)); write_csr 1124 drivers/firewire/core-transaction.c card->driver->write_csr(card, CSR_STATE_CLEAR, write_csr 92 drivers/firewire/core.h void (*write_csr)(struct fw_card *card, int csr_offset, u32 value); write_csr 3510 drivers/firewire/ohci.c .write_csr = ohci_write_csr, write_csr 1381 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, csr, value); write_csr 5706 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_INFO, info); write_csr 6122 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : write_csr 6158 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : write_csr 6213 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, write_csr 6224 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, write_csr 6347 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, write_csr 6369 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); write_csr 6390 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); write_csr 6396 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); write_csr 6424 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); write_csr 6445 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); write_csr 6447 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf write_csr 6461 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); write_csr 6462 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CREDIT_VL15, 0); write_csr 6463 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); write_csr 6502 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_RUN, 0); write_csr 6504 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, write_csr 6509 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, reg | write_csr 6514 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, reg); write_csr 6515 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); write_csr 6544 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_RST, 0x1); write_csr 6568 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_RST, 0ull); write_csr 6575 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); write_csr 6577 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); write_csr 6655 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); write_csr 6666 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); write_csr 6668 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, write_csr 6670 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); write_csr 6743 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_CTRL, rcvctrl); write_csr 6768 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); write_csr 6917 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); write_csr 6921 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); write_csr 6923 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); write_csr 7520 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_CRC_MODE, write_csr 7526 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CTRL, write_csr 7529 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CTRL, write_csr 7590 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); write_csr 7594 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); write_csr 7597 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ write_csr 7865 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_ERR_EN, write_csr 8328 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); write_csr 8361 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, write_csr 8384 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, rcd->imask); write_csr 8392 drivers/infiniband/hw/hfi1/chip.c write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); write_csr 8525 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_PORT_CONFIG, reg); write_csr 8633 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, data); write_csr 8663 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, data); write_csr 8736 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); write_csr 8747 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); write_csr 8749 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); write_csr 8786 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); write_csr 9160 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LOOPBACK, write_csr 9162 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); write_csr 9167 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); write_csr 9172 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_RUN, write_csr 9179 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, write_csr 9197 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ write_csr 9212 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ write_csr 9230 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_MODE, write_csr 9472 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, write_csr 9478 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); write_csr 9495 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, write_csr 9501 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, write_csr 9689 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, write_csr 9691 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, write_csr 9699 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, write_csr 9722 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); write_csr 9723 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); write_csr 9724 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); write_csr 9725 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); write_csr 9726 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); write_csr 9727 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); write_csr 9728 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); write_csr 10100 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_LEN_CHECK0, len1); write_csr 10101 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_LEN_CHECK1, len2); write_csr 10127 drivers/infiniband/hw/hfi1/chip.c write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); write_csr 10150 drivers/infiniband/hw/hfi1/chip.c write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); write_csr 10329 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); write_csr 10330 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, write_csr 10333 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); write_csr 10334 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); write_csr 10335 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); write_csr 10336 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); write_csr 10338 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); write_csr 10341 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); write_csr 10342 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); write_csr 10349 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); write_csr 10350 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); write_csr 10351 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); write_csr 10426 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ write_csr 10782 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_LED_CNTRL, 0); write_csr 10946 drivers/infiniband/hw/hfi1/chip.c write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); write_csr 11118 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, target + (i * 8), reg); write_csr 11214 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, write_csr 11232 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, write_csr 11268 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); write_csr 11279 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); write_csr 11296 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, reg); write_csr 11313 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, reg); write_csr 11958 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); write_csr 11961 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_VL15, 0); write_csr 13076 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK + (8 * idx), reg); write_csr 13123 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); write_csr 13125 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); write_csr 13126 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); write_csr 13127 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); write_csr 13128 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); write_csr 13129 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); write_csr 13130 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); write_csr 13131 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); write_csr 13137 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); write_csr 13138 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); write_csr 13139 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); write_csr 13167 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MAP + (8 * m), reg); write_csr 13198 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MAP + (8 * i), 0); write_csr 13421 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_PARTITION_KEY + write_csr 13445 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MAP + (8 * i), 0); write_csr 13474 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); write_csr 13492 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_CTRL, ctrl_bits); write_csr 13523 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_SCRATCH + (8 * i), 0); write_csr 13525 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_ERR_MASK, 0); write_csr 13526 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_ERR_CLEAR, ~0ull); write_csr 13529 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); write_csr 13530 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); write_csr 13533 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); write_csr 13534 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), write_csr 13539 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); write_csr 13540 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); write_csr 13543 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MAP, 0); write_csr 13546 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK + (8 * i), 0); write_csr 13547 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); write_csr 13552 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); write_csr 13561 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); write_csr 13562 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); write_csr 13563 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); write_csr 13570 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_RSA_CMD, 1); write_csr 13571 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_RSA_MU, 0); write_csr 13572 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_CFG_FW_CTRL, 0); write_csr 13578 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_ERR_MASK, 0); write_csr 13579 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_ERR_CLEAR, ~0ull); write_csr 13591 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CTRL, 0); write_csr 13597 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); write_csr 13600 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_PIO_ERR_MASK, 0); write_csr 13601 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); write_csr 13604 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_DMA_ERR_MASK, 0); write_csr 13605 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); write_csr 13608 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_MASK, 0); write_csr 13609 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); write_csr 13611 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_BTH_QP, 0); write_csr 13612 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); write_csr 13613 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT0, 0); write_csr 13614 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT1, 0); write_csr 13615 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT2, 0); write_csr 13616 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT3, 0); write_csr 13617 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_LEN_CHECK0, 0); write_csr 13618 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_LEN_CHECK1, 0); write_csr 13620 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_ERR_MASK, 0); write_csr 13621 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_ERR_CLEAR, ~0ull); write_csr 13624 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); write_csr 13626 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); write_csr 13628 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); write_csr 13630 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); write_csr 13632 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); write_csr 13633 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); write_csr 13634 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); write_csr 13636 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_TIMER_CTRL, 0); write_csr 13637 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); write_csr 13638 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); write_csr 13639 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); write_csr 13640 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); write_csr 13642 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); write_csr 13643 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_CREDIT_VL15, 0); write_csr 13648 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); write_csr 13736 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); write_csr 13773 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_CTRL, 0); write_csr 13779 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_BTH_QP, 0); write_csr 13780 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_MULTICAST, 0); write_csr 13781 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_BYPASS, 0); write_csr 13782 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_VL15, 0); write_csr 13784 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_ERR_INFO, write_csr 13787 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_ERR_MASK, 0); write_csr 13788 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_ERR_CLEAR, ~0ull); write_csr 13791 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); write_csr 13793 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); write_csr 13795 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); write_csr 13797 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); write_csr 13801 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); write_csr 13851 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( write_csr 13857 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( write_csr 13863 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( write_csr 13869 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( write_csr 13877 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( write_csr 13881 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( write_csr 13921 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CTRL, 0); write_csr 13927 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_CTRL, 0); write_csr 13929 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_CTXT_CTRL, 0); write_csr 13932 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); write_csr 13940 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); write_csr 13980 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_DC_CTRL, 0); write_csr 13995 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, ASIC_QSFP1_OUT, 0x1f); write_csr 13996 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, ASIC_QSFP2_OUT, 0x1f); write_csr 14038 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_BTH_QP, write_csr 14042 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_BTH_QP, write_csr 14092 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, regno, reg); write_csr 14152 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); write_csr 14165 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_CFG + (8 * rule_index), write_csr 14169 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), write_csr 14176 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), write_csr 14188 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); write_csr 14189 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); write_csr 14190 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); write_csr 14430 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, regoff, reg); write_csr 14474 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_ERR_MASK, ~0ull); write_csr 14505 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, RCV_BYPASS, val); write_csr 14512 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_ERR_MASK, ~0ull); write_csr 14514 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); write_csr 14516 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_ERR_FLG_EN, ~0ull); write_csr 14517 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_ERR_EN, ~0ull); write_csr 14531 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, csr0to3, write_csr 14538 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, csr4to7, write_csr 14566 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); write_csr 14567 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); write_csr 14568 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_ERR_MASK, ~0ull); write_csr 14569 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); write_csr 14585 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); write_csr 14787 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK, 0ull); write_csr 14793 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_CLEAR, all_bits); write_csr 14799 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_FORCE, all_bits); write_csr 14805 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_CLEAR, all_bits); write_csr 14806 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK, mask); write_csr 14810 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK, mask); write_csr 15231 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); write_csr 15274 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); write_csr 616 drivers/infiniband/hw/hfi1/chip.h void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value); write_csr 634 drivers/infiniband/hw/hfi1/chip.h write_csr(dd, offset0 + (0x100 * ctxt), value); write_csr 669 drivers/infiniband/hw/hfi1/chip.h write_csr(dd, offset0 + (0x1000 * ctxt), value); write_csr 621 drivers/infiniband/hw/hfi1/debugfs.c write_csr(dd, ASIC_CFG_SCRATCH, scratch0); write_csr 1097 drivers/infiniband/hw/hfi1/debugfs.c write_csr(dd, ASIC_GPIO_OUT, gpio_val); write_csr 1098 drivers/infiniband/hw/hfi1/debugfs.c write_csr(dd, ASIC_GPIO_OE, gpio_val); write_csr 1287 drivers/infiniband/hw/hfi1/driver.c write_csr(dd, DCC_CFG_LED_CNTRL, 0); write_csr 92 drivers/infiniband/hw/hfi1/eprom.c write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset)); write_csr 95 drivers/infiniband/hw/hfi1/eprom.c write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */ write_csr 193 drivers/infiniband/hw/hfi1/eprom.c write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK); write_csr 195 drivers/infiniband/hw/hfi1/eprom.c write_csr(dd, ASIC_EEP_CTL_STAT, write_csr 199 drivers/infiniband/hw/hfi1/eprom.c write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID); write_csr 280 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); write_csr 282 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, write_csr 317 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); write_csr 326 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); write_csr 349 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); write_csr 354 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); write_csr 368 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); write_csr 385 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); write_csr 386 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); write_csr 788 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, what + (8 * i), *ptr); write_csr 795 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, what + (8 * i), value); write_csr 811 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, what, *ptr); write_csr 830 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT); write_csr 846 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START); write_csr 911 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_ERR_CLEAR, write_csr 1001 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RST, reg); write_csr 1013 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RST, reg); write_csr 1021 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_FW_CTRL, 0); write_csr 1035 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK); write_csr 1043 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RST, 0ull); write_csr 1079 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SBUS_REQUEST, write_csr 1143 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK); write_csr 1153 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, MISC_CFG_FW_CTRL, 0); write_csr 1223 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SBUS_EXECUTE, write_csr 1246 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); write_csr 1412 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_MUTEX, mask); write_csr 1428 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_MUTEX, 0); write_csr 1446 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_MUTEX, 0); write_csr 1505 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit); write_csr 1567 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SCRATCH, scratch0); write_csr 1621 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SCRATCH, scratch0); write_csr 1645 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SBUS_EXECUTE, write_csr 1661 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); write_csr 2217 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, CCE_DC_CTRL, 0); write_csr 2283 drivers/infiniband/hw/hfi1/hfi.h write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); write_csr 2285 drivers/infiniband/hw/hfi1/hfi.h write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); write_csr 586 drivers/infiniband/hw/hfi1/init.c write_csr(dd, SEND_STATIC_RATE_CONTROL, src); write_csr 1804 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT0, *val++); write_csr 1805 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT1, *val++); write_csr 1806 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT2, *val++); write_csr 1807 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, SEND_SC2VLT3, *val++); write_csr 3674 drivers/infiniband/hw/hfi1/mad.c write_csr(dd, RCV_ERR_INFO, write_csr 879 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), write_csr 898 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); write_csr 973 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); write_csr 1070 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); write_csr 1296 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); write_csr 1351 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); write_csr 1373 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, CCE_DC_CTRL, 0); write_csr 1429 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); write_csr 65 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK); write_csr 123 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_CTRL, reg); write_csr 1266 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_PIO_ERR_CLEAR, write_csr 1271 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_PIO_INIT_CTXT, write_csr 1344 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_PIO_INIT_CTXT, pio); write_csr 85 drivers/infiniband/hw/hfi1/qsfp.c write_csr(dd, target_oe, reg); write_csr 109 drivers/infiniband/hw/hfi1/qsfp.c write_csr(dd, target_oe, reg); write_csr 3420 drivers/infiniband/hw/hfi1/sdma.c write_csr(sde->dd, write_csr 247 drivers/net/ethernet/amd/pcnet32.c void (*write_csr) (unsigned long, int, u16); write_csr 387 drivers/net/ethernet/amd/pcnet32.c .write_csr = pcnet32_wio_write_csr, write_csr 442 drivers/net/ethernet/amd/pcnet32.c .write_csr = pcnet32_dwio_write_csr, write_csr 468 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); write_csr 701 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); write_csr 726 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND); write_csr 774 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); write_csr 787 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR15, csr15); write_csr 901 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ write_csr 997 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ write_csr 1003 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ write_csr 1011 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ write_csr 1062 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR15, x | 0x0044); write_csr 1065 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ write_csr 1084 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ write_csr 1120 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ write_csr 1412 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ write_csr 1421 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); write_csr 1424 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); write_csr 1723 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, 80, write_csr 1918 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); write_csr 1919 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); write_csr 1934 drivers/net/ethernet/amd/pcnet32.c a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); write_csr 2158 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, 124, val); write_csr 2262 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); write_csr 2278 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); write_csr 2279 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); write_csr 2281 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ write_csr 2282 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); write_csr 2300 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); write_csr 2449 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); write_csr 2455 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, csr0_bits); write_csr 2468 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); write_csr 2546 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); write_csr 2577 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); write_csr 2610 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR3, val); write_csr 2647 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); write_csr 2697 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); write_csr 2698 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); write_csr 2699 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); write_csr 2700 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); write_csr 2714 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, write_csr 2736 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); write_csr 2740 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); write_csr 2747 drivers/net/ethernet/amd/pcnet32.c lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);