write_aux_reg      74 arch/arc/include/asm/cmpxchg.h 	write_aux_reg(CTOP_AUX_GPA1, expected);
write_aux_reg      83 arch/arc/include/asm/irqflags-arcv2.h 		write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff);
write_aux_reg     134 arch/arc/include/asm/irqflags-arcv2.h 	write_aux_reg(AUX_IRQ_HINT, irq);
write_aux_reg     139 arch/arc/include/asm/irqflags-arcv2.h 	write_aux_reg(AUX_IRQ_HINT, 0);
write_aux_reg      96 arch/arc/include/asm/mmu_context.h 	write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE);
write_aux_reg     149 arch/arc/include/asm/mmu_context.h 	write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
write_aux_reg      80 arch/arc/kernel/intc-arcv2.c 		write_aux_reg(AUX_IRQ_SELECT, i);
write_aux_reg      81 arch/arc/kernel/intc-arcv2.c 		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
write_aux_reg      89 arch/arc/kernel/intc-arcv2.c 			write_aux_reg(AUX_IRQ_ENABLE, 0);
write_aux_reg     101 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
write_aux_reg     102 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_ENABLE, 0);
write_aux_reg     107 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
write_aux_reg     108 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_ENABLE, 1);
write_aux_reg     114 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
write_aux_reg     115 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
write_aux_reg     122 arch/arc/kernel/intc-arcv2.c 	write_aux_reg(AUX_IRQ_ENABLE, 1);
write_aux_reg      35 arch/arc/kernel/intc-compact.c 	write_aux_reg(AUX_IRQ_LEV, level_mask);
write_aux_reg      49 arch/arc/kernel/intc-compact.c 		write_aux_reg(AUX_IENABLE, ienb);
write_aux_reg      70 arch/arc/kernel/intc-compact.c 	write_aux_reg(AUX_IENABLE, ienb);
write_aux_reg      79 arch/arc/kernel/intc-compact.c 	write_aux_reg(AUX_IENABLE, ienb);
write_aux_reg     109 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
write_aux_reg     111 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
write_aux_reg     232 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
write_aux_reg     240 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
write_aux_reg     273 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
write_aux_reg     276 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));
write_aux_reg     277 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));
write_aux_reg     306 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_CTRL,
write_aux_reg     310 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_INDEX, idx);		/* counter # */
write_aux_reg     311 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);	/* condition */
write_aux_reg     325 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
write_aux_reg     326 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_CTRL,
write_aux_reg     332 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INDEX, idx);
write_aux_reg     335 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_CONFIG, 0);
write_aux_reg     373 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
write_aux_reg     379 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_CNTL,
write_aux_reg     381 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_CNTH,
write_aux_reg     385 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);
write_aux_reg     386 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);
write_aux_reg     387 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);
write_aux_reg     423 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
write_aux_reg     430 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_PCT_INT_CTRL,
write_aux_reg     469 arch/arc/kernel/perf_event.c 	write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
write_aux_reg     616 arch/arc/kernel/perf_event.c 		write_aux_reg(ARC_REG_CC_INDEX, i);
write_aux_reg     281 arch/arc/mm/cache.c 		write_aux_reg(aux_cmd, paddr);
write_aux_reg     327 arch/arc/mm/cache.c 		write_aux_reg(aux_tag, paddr);
write_aux_reg     337 arch/arc/mm/cache.c 		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
write_aux_reg     341 arch/arc/mm/cache.c 			write_aux_reg(aux_tag, paddr);
write_aux_reg     345 arch/arc/mm/cache.c 		write_aux_reg(aux_cmd, vaddr);
write_aux_reg     403 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
write_aux_reg     405 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
write_aux_reg     409 arch/arc/mm/cache.c 		write_aux_reg(aux_cmd, paddr);
write_aux_reg     449 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
write_aux_reg     451 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
write_aux_reg     455 arch/arc/mm/cache.c 	write_aux_reg(e, paddr + sz);	/* ENDR is exclusive */
write_aux_reg     456 arch/arc/mm/cache.c 	write_aux_reg(s, paddr);
write_aux_reg     491 arch/arc/mm/cache.c 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
write_aux_reg     515 arch/arc/mm/cache.c 	write_aux_reg(ctl, val);
write_aux_reg     533 arch/arc/mm/cache.c 			write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
write_aux_reg     554 arch/arc/mm/cache.c 	write_aux_reg(aux, 0x1);
write_aux_reg     564 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
write_aux_reg     571 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
write_aux_reg     611 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_IC_IVIC, 1);
write_aux_reg     702 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
write_aux_reg     711 arch/arc/mm/cache.c 		write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
write_aux_reg     713 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
write_aux_reg     716 arch/arc/mm/cache.c 		write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
write_aux_reg     718 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
write_aux_reg     756 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
write_aux_reg     766 arch/arc/mm/cache.c 		write_aux_reg(cmd, paddr);
write_aux_reg     792 arch/arc/mm/cache.c 	write_aux_reg(r, ctrl);
write_aux_reg     795 arch/arc/mm/cache.c 		write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
write_aux_reg     797 arch/arc/mm/cache.c 		write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
write_aux_reg     811 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
write_aux_reg     818 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
write_aux_reg    1193 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);
write_aux_reg    1201 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
write_aux_reg    1202 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);
write_aux_reg    1203 arch/arc/mm/cache.c 	write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);
write_aux_reg    1320 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
write_aux_reg    1323 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
write_aux_reg    1326 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
write_aux_reg    1327 arch/arc/mm/cache.c 			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);
write_aux_reg     112 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD1, 0);
write_aux_reg     115 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBPD1HI, 0);
write_aux_reg     117 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD0, 0);
write_aux_reg     118 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
write_aux_reg     127 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
write_aux_reg     129 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
write_aux_reg     182 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBINDEX, 0xa);
write_aux_reg     185 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
write_aux_reg     207 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
write_aux_reg     210 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD1, pd1);
write_aux_reg     217 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
write_aux_reg     229 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
write_aux_reg     230 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
write_aux_reg     235 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD0, pd0);
write_aux_reg     236 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD1, pd1);
write_aux_reg     239 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
write_aux_reg     241 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
write_aux_reg     260 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD1, 0);
write_aux_reg     263 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBPD1HI, 0);
write_aux_reg     265 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_TLBPD0, 0);
write_aux_reg     269 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBINDEX, entry);
write_aux_reg     270 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
write_aux_reg     277 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
write_aux_reg     280 arch/arc/mm/tlb.c 			write_aux_reg(ARC_REG_TLBINDEX, entry);
write_aux_reg     281 arch/arc/mm/tlb.c 			write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
write_aux_reg     868 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_PID, MMU_ENABLE);
write_aux_reg     873 arch/arc/mm/tlb.c 	write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
write_aux_reg     877 arch/arc/mm/tlb.c 		write_aux_reg(ARC_REG_TLBPD1HI, 0);
write_aux_reg     927 arch/arc/mm/tlb.c 			write_aux_reg(ARC_REG_TLBINDEX,
write_aux_reg     929 arch/arc/mm/tlb.c 			write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
write_aux_reg     960 arch/arc/mm/tlb.c 				write_aux_reg(ARC_REG_TLBINDEX,
write_aux_reg      17 arch/arc/plat-eznps/ctop.c 	write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
write_aux_reg      20 arch/arc/plat-eznps/ctop.c 	write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
write_aux_reg      45 arch/arc/plat-eznps/mtm.c 	write_aux_reg(CTOP_AUX_UDMC, udmc.value);
write_aux_reg     115 arch/arc/plat-eznps/mtm.c 	write_aux_reg(CTOP_AUX_DPC, dpc.value);
write_aux_reg     138 arch/arc/plat-eznps/mtm.c 	write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
write_aux_reg      66 arch/arc/plat-eznps/smp.c 	write_aux_reg(CTOP_AUX_HW_COMPLY, hw_comply.value);
write_aux_reg      70 arch/arc/plat-eznps/smp.c 	write_aux_reg(CTOP_AUX_LPC, lpc.value);
write_aux_reg      27 arch/arc/plat-hsdk/platform.c 		write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
write_aux_reg      34 arch/arc/plat-hsdk/platform.c 		write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
write_aux_reg     182 drivers/clocksource/arc_timer.c 	write_aux_reg(AUX_RTC_CTRL, 1);
write_aux_reg     226 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
write_aux_reg     227 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
write_aux_reg     228 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
write_aux_reg     245 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
write_aux_reg     246 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER0_CNT, 0);	/* start from 0 */
write_aux_reg     248 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
write_aux_reg     297 drivers/clocksource/arc_timer.c 	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
write_aux_reg     149 drivers/clocksource/timer-nps.c 	write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
write_aux_reg     153 drivers/clocksource/timer-nps.c 		write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
write_aux_reg     155 drivers/clocksource/timer-nps.c 		write_aux_reg(NPS_REG_TIMER0_CTRL,
write_aux_reg     172 drivers/clocksource/timer-nps.c 	write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
write_aux_reg     175 drivers/clocksource/timer-nps.c 	write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
write_aux_reg     176 drivers/clocksource/timer-nps.c 	write_aux_reg(NPS_REG_TIMER0_CNT, 0);
write_aux_reg     177 drivers/clocksource/timer-nps.c 	write_aux_reg(NPS_REG_TIMER0_CTRL,
write_aux_reg      63 drivers/irqchip/irq-eznps.c 	write_aux_reg(AUX_IENABLE, ienb);
write_aux_reg      73 drivers/irqchip/irq-eznps.c 	write_aux_reg(AUX_IENABLE, ienb);
write_aux_reg      80 drivers/irqchip/irq-eznps.c 	write_aux_reg(CTOP_AUX_IACK, 1 << irq);
write_aux_reg      92 drivers/irqchip/irq-eznps.c 	write_aux_reg(CTOP_AUX_IACK, 1 << irq);
write_aux_reg      51 include/soc/arc/aux.h 		write_aux_reg(reg, tmp);		\
write_aux_reg     119 include/soc/arc/mcip.h 	write_aux_reg(ARC_REG_MCIP_WDATA, data);