wr_cio_state      575 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, i);
wr_cio_state      710 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
wr_cio_state      711 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
wr_cio_state      712 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
wr_cio_state      713 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
wr_cio_state      714 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
wr_cio_state      715 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
wr_cio_state      716 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
wr_cio_state      717 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
wr_cio_state      718 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
wr_cio_state      721 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
wr_cio_state      724 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, 0x9f);
wr_cio_state      726 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
wr_cio_state      727 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
wr_cio_state      728 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
wr_cio_state      729 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
wr_cio_state      732 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
wr_cio_state      734 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
wr_cio_state      735 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
wr_cio_state      737 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
wr_cio_state      738 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
wr_cio_state      739 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
wr_cio_state      740 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
wr_cio_state      757 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
wr_cio_state      758 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
wr_cio_state      759 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
wr_cio_state      763 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
wr_cio_state      764 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
wr_cio_state      766 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
wr_cio_state      767 drivers/gpu/drm/nouveau/dispnv04/hw.c 		wr_cio_state(dev, head, regp, NV_CIO_CRE_86);