wp 688 arch/arm/kernel/hw_breakpoint.c struct perf_event *wp, **slots; wp 697 arch/arm/kernel/hw_breakpoint.c wp = slots[i]; wp 699 arch/arm/kernel/hw_breakpoint.c if (wp == NULL) wp 702 arch/arm/kernel/hw_breakpoint.c info = counter_arch_bp(wp); wp 711 arch/arm/kernel/hw_breakpoint.c info->trigger = wp->attr.bp_addr; wp 733 arch/arm/kernel/hw_breakpoint.c if (!(access & hw_breakpoint_type(wp))) wp 742 arch/arm/kernel/hw_breakpoint.c perf_bp_event(wp, regs); wp 749 arch/arm/kernel/hw_breakpoint.c if (is_default_overflow_handler(wp)) wp 750 arch/arm/kernel/hw_breakpoint.c enable_single_step(wp, instruction_pointer(regs)); wp 760 arch/arm/kernel/hw_breakpoint.c struct perf_event *wp, **slots; wp 768 arch/arm/kernel/hw_breakpoint.c wp = slots[i]; wp 770 arch/arm/kernel/hw_breakpoint.c if (wp == NULL) wp 773 arch/arm/kernel/hw_breakpoint.c info = counter_arch_bp(wp); wp 782 arch/arm/kernel/hw_breakpoint.c disable_single_step(wp); wp 740 arch/arm64/kernel/hw_breakpoint.c struct perf_event *wp, **slots; wp 754 arch/arm64/kernel/hw_breakpoint.c wp = slots[i]; wp 755 arch/arm64/kernel/hw_breakpoint.c if (wp == NULL) wp 764 arch/arm64/kernel/hw_breakpoint.c if (!(access & hw_breakpoint_type(wp))) wp 780 arch/arm64/kernel/hw_breakpoint.c info = counter_arch_bp(wp); wp 782 arch/arm64/kernel/hw_breakpoint.c perf_bp_event(wp, regs); wp 785 arch/arm64/kernel/hw_breakpoint.c if (is_default_overflow_handler(wp)) wp 790 arch/arm64/kernel/hw_breakpoint.c wp = slots[closest_match]; wp 791 arch/arm64/kernel/hw_breakpoint.c info = counter_arch_bp(wp); wp 793 arch/arm64/kernel/hw_breakpoint.c perf_bp_event(wp, regs); wp 796 arch/arm64/kernel/hw_breakpoint.c if (is_default_overflow_handler(wp)) wp 147 arch/ia64/kernel/patch.c u64 *wp; wp 160 arch/ia64/kernel/patch.c wp = (u64 *) ia64_imva((char *) offp + *offp); wp 161 arch/ia64/kernel/patch.c wp[0] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */ wp 162 arch/ia64/kernel/patch.c wp[1] = 0x0084006880000200UL; wp 163 arch/ia64/kernel/patch.c wp[2] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */ wp 164 arch/ia64/kernel/patch.c wp[3] = 0x0004000000000200UL; wp 165 arch/ia64/kernel/patch.c ia64_fc(wp); ia64_fc(wp + 2); wp 661 arch/powerpc/lib/sstep.c const unsigned int *wp; wp 706 arch/powerpc/lib/sstep.c wp = mem; wp 709 arch/powerpc/lib/sstep.c reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); wp 746 arch/powerpc/lib/sstep.c unsigned int *wp; wp 789 arch/powerpc/lib/sstep.c wp = mem; wp 792 arch/powerpc/lib/sstep.c *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); wp 108 arch/powerpc/math-emu/math_efp.c u32 wp[2]; wp 199 arch/powerpc/math-emu/math_efp.c vc.wp[0] = current->thread.evr[fc]; wp 200 arch/powerpc/math-emu/math_efp.c vc.wp[1] = regs->gpr[fc]; wp 201 arch/powerpc/math-emu/math_efp.c va.wp[0] = current->thread.evr[fa]; wp 202 arch/powerpc/math-emu/math_efp.c va.wp[1] = regs->gpr[fa]; wp 203 arch/powerpc/math-emu/math_efp.c vb.wp[0] = current->thread.evr[fb]; wp 204 arch/powerpc/math-emu/math_efp.c vb.wp[1] = regs->gpr[fb]; wp 209 arch/powerpc/math-emu/math_efp.c pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); wp 210 arch/powerpc/math-emu/math_efp.c pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); wp 211 arch/powerpc/math-emu/math_efp.c pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); wp 220 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA, va.wp + 1); wp 222 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SB, vb.wp + 1); wp 225 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA, va.wp + 1); wp 234 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; wp 238 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] | SIGN_BIT_S; wp 242 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; wp 276 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 280 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, wp 300 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 303 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, wp 311 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 314 arch/powerpc/math-emu/math_efp.c FP_TO_INT_S(vc.wp[1], SB, 32, wp 327 arch/powerpc/math-emu/math_efp.c FP_PACK_SP(vc.wp + 1, SR); wp 406 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 410 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, wp 418 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SB, vb.wp + 1); wp 441 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 444 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, wp 452 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 455 arch/powerpc/math-emu/math_efp.c FP_TO_INT_D(vc.wp[1], DB, 32, wp 493 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA0, va.wp); wp 494 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA1, va.wp + 1); wp 496 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SB0, vb.wp); wp 497 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SB1, vb.wp + 1); wp 500 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA0, va.wp); wp 501 arch/powerpc/math-emu/math_efp.c FP_UNPACK_SP(SA1, va.wp + 1); wp 516 arch/powerpc/math-emu/math_efp.c vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; wp 517 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; wp 521 arch/powerpc/math-emu/math_efp.c vc.wp[0] = va.wp[0] | SIGN_BIT_S; wp 522 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] | SIGN_BIT_S; wp 526 arch/powerpc/math-emu/math_efp.c vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; wp 527 arch/powerpc/math-emu/math_efp.c vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; wp 565 arch/powerpc/math-emu/math_efp.c vc.wp[0] = 0; wp 569 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, wp 573 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 577 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, wp 585 arch/powerpc/math-emu/math_efp.c vc.wp[0] = 0; wp 588 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, wp 592 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 595 arch/powerpc/math-emu/math_efp.c FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, wp 603 arch/powerpc/math-emu/math_efp.c vc.wp[0] = 0; wp 606 arch/powerpc/math-emu/math_efp.c FP_TO_INT_S(vc.wp[0], SB0, 32, wp 610 arch/powerpc/math-emu/math_efp.c vc.wp[1] = 0; wp 613 arch/powerpc/math-emu/math_efp.c FP_TO_INT_S(vc.wp[1], SB1, 32, wp 629 arch/powerpc/math-emu/math_efp.c FP_PACK_SP(vc.wp, SR0); wp 630 arch/powerpc/math-emu/math_efp.c FP_PACK_SP(vc.wp + 1, SR1); wp 681 arch/powerpc/math-emu/math_efp.c current->thread.evr[fc] = vc.wp[0]; wp 682 arch/powerpc/math-emu/math_efp.c regs->gpr[fc] = vc.wp[1]; wp 687 arch/powerpc/math-emu/math_efp.c pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); wp 688 arch/powerpc/math-emu/math_efp.c pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); wp 689 arch/powerpc/math-emu/math_efp.c pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); wp 753 arch/powerpc/math-emu/math_efp.c fgpr.wp[0] = current->thread.evr[fc]; wp 754 arch/powerpc/math-emu/math_efp.c fgpr.wp[1] = regs->gpr[fc]; wp 787 arch/powerpc/math-emu/math_efp.c if (fgpr.wp[1] == 0) wp 795 arch/powerpc/math-emu/math_efp.c if (fgpr.wp[1] == 0) wp 797 arch/powerpc/math-emu/math_efp.c if (fgpr.wp[0] == 0) wp 806 arch/powerpc/math-emu/math_efp.c if (fgpr.wp[1] == 0) wp 815 arch/powerpc/math-emu/math_efp.c pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); wp 824 arch/powerpc/math-emu/math_efp.c if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ wp 828 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]++; /* Z < 0, choose Z2 */ wp 830 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]--; /* Z < 0, choose Z2 */ wp 841 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]++; /* Z > 0, choose Z1 */ wp 848 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]--; /* Z < 0, choose Z2 */ wp 856 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ wp 858 arch/powerpc/math-emu/math_efp.c fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ wp 862 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ wp 864 arch/powerpc/math-emu/math_efp.c fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ wp 868 arch/powerpc/math-emu/math_efp.c fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ wp 870 arch/powerpc/math-emu/math_efp.c fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ wp 879 arch/powerpc/math-emu/math_efp.c current->thread.evr[fc] = fgpr.wp[0]; wp 880 arch/powerpc/math-emu/math_efp.c regs->gpr[fc] = fgpr.wp[1]; wp 882 arch/powerpc/math-emu/math_efp.c pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); wp 58 arch/powerpc/platforms/pseries/dtl.c struct dtl_entry *wp = dtlr->write_ptr; wp 61 arch/powerpc/platforms/pseries/dtl.c if (!wp) wp 64 arch/powerpc/platforms/pseries/dtl.c *wp = *dtle; wp 71 arch/powerpc/platforms/pseries/dtl.c ++wp; wp 72 arch/powerpc/platforms/pseries/dtl.c if (wp == dtlr->buf_end) wp 73 arch/powerpc/platforms/pseries/dtl.c wp = dtlr->buf; wp 74 arch/powerpc/platforms/pseries/dtl.c dtlr->write_ptr = wp; wp 57 arch/s390/include/asm/nmi.h u64 wp : 1; /* 20 psw mwp validity */ wp 276 arch/s390/kernel/nmi.c if (!mci.wp) { wp 4853 arch/x86/kvm/mmu.c bool wp; wp 4866 arch/x86/kvm/mmu.c wp = is_write_protection(vcpu); wp 4889 arch/x86/kvm/mmu.c check_write = check_pkey && wf && (uf || wp); wp 116 block/blk-zoned.c rep->wp = rep->start + rep->len; wp 118 block/blk-zoned.c rep->wp -= offset; wp 210 drivers/acpi/resource.c bool wp = addr->info.mem.write_protect; wp 251 drivers/acpi/resource.c acpi_dev_memresource_flags(res, len, wp); wp 3667 drivers/ata/libata-scsi.c u64 size, start, wp; wp 3677 drivers/ata/libata-scsi.c wp = get_unaligned_le64(&rec[24]); wp 3682 drivers/ata/libata-scsi.c put_unaligned_be64(wp, &rec[24]); wp 585 drivers/atm/firestream.c u32 wp; wp 591 drivers/atm/firestream.c while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) { wp 597 drivers/atm/firestream.c wp &= ~0xf; wp 598 drivers/atm/firestream.c cqe = bus_to_virt (wp); wp 609 drivers/atm/firestream.c int rp, wp; wp 611 drivers/atm/firestream.c wp = read_fs (dev, Q_WP(q->offset)); wp 613 drivers/atm/firestream.c q->offset, rp, wp, wp-rp); wp 222 drivers/block/drbd/drbd_proc.c char wp; wp 271 drivers/block/drbd/drbd_proc.c wp = nc ? nc->wire_protocol - DRBD_PROT_A + 'A' : ' '; wp 281 drivers/block/drbd/drbd_proc.c wp, wp 47 drivers/block/null_blk_zoned.c zone->wp = zone->start + zone->len; wp 57 drivers/block/null_blk_zoned.c zone->start = zone->wp = sector; wp 106 drivers/block/null_blk_zoned.c if (sector != zone->wp) wp 112 drivers/block/null_blk_zoned.c zone->wp += nr_sectors; wp 113 drivers/block/null_blk_zoned.c if (zone->wp == zone->start + zone->len) wp 138 drivers/block/null_blk_zoned.c zone[i].wp = zone[i].start; wp 146 drivers/block/null_blk_zoned.c zone->wp = zone->start; wp 1655 drivers/block/pktcdvd.c write_param_page *wp; wp 1664 drivers/block/pktcdvd.c init_cdrom_command(&cgc, buffer, sizeof(*wp), CGC_DATA_READ); wp 1691 drivers/block/pktcdvd.c wp = (write_param_page *) &buffer[sizeof(struct mode_page_header) + pd->mode_offset]; wp 1693 drivers/block/pktcdvd.c wp->fp = pd->settings.fp; wp 1694 drivers/block/pktcdvd.c wp->track_mode = pd->settings.track_mode; wp 1695 drivers/block/pktcdvd.c wp->write_type = pd->settings.write_type; wp 1696 drivers/block/pktcdvd.c wp->data_block_type = pd->settings.block_mode; wp 1698 drivers/block/pktcdvd.c wp->multi_session = 0; wp 1701 drivers/block/pktcdvd.c wp->link_size = 7; wp 1702 drivers/block/pktcdvd.c wp->ls_v = 1; wp 1705 drivers/block/pktcdvd.c if (wp->data_block_type == PACKET_BLOCK_MODE1) { wp 1706 drivers/block/pktcdvd.c wp->session_format = 0; wp 1707 drivers/block/pktcdvd.c wp->subhdr2 = 0x20; wp 1708 drivers/block/pktcdvd.c } else if (wp->data_block_type == PACKET_BLOCK_MODE2) { wp 1709 drivers/block/pktcdvd.c wp->session_format = 0x20; wp 1710 drivers/block/pktcdvd.c wp->subhdr2 = 8; wp 1712 drivers/block/pktcdvd.c wp->mcn[0] = 0x80; wp 1713 drivers/block/pktcdvd.c memcpy(&wp->mcn[1], PACKET_MCN, sizeof(wp->mcn) - 1); wp 1719 drivers/block/pktcdvd.c pkt_err(pd, "write mode wrong %d\n", wp->data_block_type); wp 1722 drivers/block/pktcdvd.c wp->packet_size = cpu_to_be32(pd->settings.size >> 2); wp 3937 drivers/gpu/drm/i915/intel_pm.c u32 plane_pixel_rate, struct skl_wm_params *wp, wp 3941 drivers/gpu/drm/i915/intel_pm.c const struct skl_wm_params *wp, wp 3953 drivers/gpu/drm/i915/intel_pm.c struct skl_wm_params wp; wp 3959 drivers/gpu/drm/i915/intel_pm.c crtc_state->pixel_rate, &wp, 0); wp 3963 drivers/gpu/drm/i915/intel_pm.c skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); wp 4642 drivers/gpu/drm/i915/intel_pm.c u32 plane_pixel_rate, struct skl_wm_params *wp, wp 4655 drivers/gpu/drm/i915/intel_pm.c wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || wp 4659 drivers/gpu/drm/i915/intel_pm.c wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; wp 4660 drivers/gpu/drm/i915/intel_pm.c wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || wp 4662 drivers/gpu/drm/i915/intel_pm.c wp->is_planar = is_planar_yuv_format(format->format); wp 4664 drivers/gpu/drm/i915/intel_pm.c wp->width = width; wp 4665 drivers/gpu/drm/i915/intel_pm.c if (color_plane == 1 && wp->is_planar) wp 4666 drivers/gpu/drm/i915/intel_pm.c wp->width /= 2; wp 4668 drivers/gpu/drm/i915/intel_pm.c wp->cpp = format->cpp[color_plane]; wp 4669 drivers/gpu/drm/i915/intel_pm.c wp->plane_pixel_rate = plane_pixel_rate; wp 4672 drivers/gpu/drm/i915/intel_pm.c modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) wp 4673 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size = 256; wp 4675 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size = 512; wp 4678 drivers/gpu/drm/i915/intel_pm.c switch (wp->cpp) { wp 4680 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines = 16; wp 4683 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines = 8; wp 4686 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines = 4; wp 4689 drivers/gpu/drm/i915/intel_pm.c MISSING_CASE(wp->cpp); wp 4693 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines = 4; wp 4697 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines *= 2; wp 4699 drivers/gpu/drm/i915/intel_pm.c wp->plane_bytes_per_line = wp->width * wp->cpp; wp 4700 drivers/gpu/drm/i915/intel_pm.c if (wp->y_tiled) { wp 4701 drivers/gpu/drm/i915/intel_pm.c interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * wp 4702 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines, wp 4703 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size); wp 4708 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line = div_fixed16(interm_pbpl, wp 4709 drivers/gpu/drm/i915/intel_pm.c wp->y_min_scanlines); wp 4710 drivers/gpu/drm/i915/intel_pm.c } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) { wp 4711 drivers/gpu/drm/i915/intel_pm.c interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, wp 4712 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size); wp 4713 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); wp 4715 drivers/gpu/drm/i915/intel_pm.c interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, wp 4716 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size) + 1; wp 4717 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); wp 4720 drivers/gpu/drm/i915/intel_pm.c wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, wp 4721 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line); wp 4723 drivers/gpu/drm/i915/intel_pm.c wp->linetime_us = fixed16_to_u32_round_up( wp 4732 drivers/gpu/drm/i915/intel_pm.c struct skl_wm_params *wp, int color_plane) wp 4753 drivers/gpu/drm/i915/intel_pm.c wp, color_plane); wp 4767 drivers/gpu/drm/i915/intel_pm.c const struct skl_wm_params *wp, wp 4791 drivers/gpu/drm/i915/intel_pm.c if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled) wp 4794 drivers/gpu/drm/i915/intel_pm.c method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate, wp 4795 drivers/gpu/drm/i915/intel_pm.c wp->cpp, latency, wp->dbuf_block_size); wp 4796 drivers/gpu/drm/i915/intel_pm.c method2 = skl_wm_method2(wp->plane_pixel_rate, wp 4799 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line); wp 4801 drivers/gpu/drm/i915/intel_pm.c if (wp->y_tiled) { wp 4802 drivers/gpu/drm/i915/intel_pm.c selected_result = max_fixed16(method2, wp->y_tile_minimum); wp 4804 drivers/gpu/drm/i915/intel_pm.c if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal / wp 4805 drivers/gpu/drm/i915/intel_pm.c wp->dbuf_block_size < 1) && wp 4806 drivers/gpu/drm/i915/intel_pm.c (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { wp 4808 drivers/gpu/drm/i915/intel_pm.c } else if (latency >= wp->linetime_us) { wp 4821 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line); wp 4825 drivers/gpu/drm/i915/intel_pm.c if (level == 0 && wp->rc_surface) wp 4827 drivers/gpu/drm/i915/intel_pm.c fixed16_to_u32_round_up(wp->y_tile_minimum); wp 4831 drivers/gpu/drm/i915/intel_pm.c if (wp->y_tiled) { wp 4833 drivers/gpu/drm/i915/intel_pm.c fixed16_to_u32_round_up(wp->y_tile_minimum); wp 4834 drivers/gpu/drm/i915/intel_pm.c res_lines += wp->y_min_scanlines; wp 4851 drivers/gpu/drm/i915/intel_pm.c if (wp->y_tiled) { wp 4854 drivers/gpu/drm/i915/intel_pm.c if (res_lines % wp->y_min_scanlines == 0) wp 4855 drivers/gpu/drm/i915/intel_pm.c extra_lines = wp->y_min_scanlines; wp 4857 drivers/gpu/drm/i915/intel_pm.c extra_lines = wp->y_min_scanlines * 2 - wp 4858 drivers/gpu/drm/i915/intel_pm.c res_lines % wp->y_min_scanlines; wp 4861 drivers/gpu/drm/i915/intel_pm.c wp->plane_blocks_per_line); wp 4928 drivers/gpu/drm/i915/intel_pm.c const struct skl_wm_params *wp, wp 4963 drivers/gpu/drm/i915/intel_pm.c if (wp->y_tiled) { wp 4965 drivers/gpu/drm/i915/intel_pm.c (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); wp 238 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_wp_data *wp; wp 260 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_wp_data *wp; wp 295 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_video_start(struct hdmi_wp_data *wp); wp 296 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_video_stop(struct hdmi_wp_data *wp); wp 297 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); wp 298 drivers/gpu/drm/omapdrm/dss/hdmi.h u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); wp 299 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); wp 300 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); wp 301 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); wp 302 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); wp 303 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); wp 304 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, wp 306 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, wp 308 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, wp 312 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, wp 314 drivers/gpu/drm/omapdrm/dss/hdmi.h phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); wp 319 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); wp 336 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); wp 337 drivers/gpu/drm/omapdrm/dss/hdmi.h int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); wp 338 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, wp 340 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, wp 355 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_wp_data wp; wp 64 drivers/gpu/drm/omapdrm/dss/hdmi4.c struct hdmi_wp_data *wp = &hdmi->wp; wp 67 drivers/gpu/drm/omapdrm/dss/hdmi4.c irqstatus = hdmi_wp_get_irqstatus(wp); wp 68 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, irqstatus); wp 78 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); wp 80 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | wp 83 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 85 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); wp 87 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 147 drivers/gpu/drm/omapdrm/dss/hdmi4.c struct hdmi_wp_data *wp = &hdmi->wp; wp 156 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); wp 157 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE); wp 193 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 197 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi4_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg); wp 203 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi_wp_video_start(&hdmi->wp); wp 207 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_irqenable(wp, wp 215 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF); wp 227 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_clear_irqenable(&hdmi->wp, ~HDMI_IRQ_CORE); wp 229 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_video_stop(&hdmi->wp); wp 233 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF); wp 265 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_dump(&hdmi->wp, s); wp 294 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_audio_enable(&hd->wp, true); wp 295 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi4_audio_start(&hd->core, &hd->wp); wp 300 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi4_audio_stop(&hd->core, &hd->wp); wp 301 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_wp_audio_enable(&hd->wp, false); wp 321 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi4_audio_config(&hdmi->core, &hdmi->wp, wp 555 drivers/gpu/drm/omapdrm/dss/hdmi4.c ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, wp 582 drivers/gpu/drm/omapdrm/dss/hdmi4.c .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp), wp 612 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp); wp 616 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi4_cec_init(hdmi->pdev, &hdmi->core, &hdmi->wp); wp 733 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi_wp_init(pdev, &hdmi->wp, 4); wp 176 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); wp 177 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); wp 178 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); wp 190 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); wp 213 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); wp 250 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); wp 338 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c struct hdmi_wp_data *wp) wp 349 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c core->wp = wp; wp 352 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); wp 32 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h struct hdmi_wp_data *wp); wp 45 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h struct hdmi_wp_data *wp) wp 298 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c struct hdmi_wp_data *wp, struct hdmi_config *cfg) wp 311 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_video_config_timing(wp, &vm); wp 316 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_video_config_format(wp, &video_format); wp 318 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_video_config_interface(wp, &vm); wp 672 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 842 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_audio_config_dma(wp, &audio_dma); wp 843 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_audio_config_format(wp, &audio_format); wp 854 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) wp 859 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_audio_core_req_enable(wp, true); wp 864 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) wp 869 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_wp_audio_core_req_enable(wp, false); wp 253 drivers/gpu/drm/omapdrm/dss/hdmi4_core.h void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 262 drivers/gpu/drm/omapdrm/dss/hdmi4_core.h int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); wp 263 drivers/gpu/drm/omapdrm/dss/hdmi4_core.h void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); wp 264 drivers/gpu/drm/omapdrm/dss/hdmi4_core.h int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 65 drivers/gpu/drm/omapdrm/dss/hdmi5.c struct hdmi_wp_data *wp = &hdmi->wp; wp 68 drivers/gpu/drm/omapdrm/dss/hdmi5.c irqstatus = hdmi_wp_get_irqstatus(wp); wp 69 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_irqstatus(wp, irqstatus); wp 81 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); wp 93 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | wp 96 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 101 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); wp 103 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 169 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); wp 170 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_irqstatus(&hdmi->wp, wp 171 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_get_irqstatus(&hdmi->wp)); wp 192 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON); wp 196 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg); wp 202 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi_wp_video_start(&hdmi->wp); wp 206 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_irqenable(&hdmi->wp, wp 214 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF); wp 226 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); wp 228 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_video_stop(&hdmi->wp); wp 232 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF); wp 264 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_dump(&hdmi->wp, s); wp 284 drivers/gpu/drm/omapdrm/dss/hdmi5.c idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); wp 286 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); wp 290 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); wp 300 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); wp 301 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_audio_enable(&hd->wp, true); wp 302 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_audio_core_req_enable(&hd->wp, true); wp 307 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_audio_core_req_enable(&hd->wp, false); wp 308 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_wp_audio_enable(&hd->wp, false); wp 309 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); wp 329 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi5_audio_config(&hdmi->core, &hdmi->wp, wp 549 drivers/gpu/drm/omapdrm/dss/hdmi5.c ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, wp 576 drivers/gpu/drm/omapdrm/dss/hdmi5.c .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp), wp 589 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); wp 607 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp); wp 717 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi_wp_init(pdev, &hdmi->wp, 5); wp 597 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 610 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_wp_video_config_timing(wp, &vm); wp 615 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_wp_video_config_format(wp, &video_format); wp 617 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_wp_video_config_interface(wp, &vm); wp 795 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 884 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_wp_audio_config_dma(wp, &audio_dma); wp 885 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_wp_audio_config_format(wp, &audio_format); wp 287 drivers/gpu/drm/omapdrm/dss/hdmi5_core.h void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 291 drivers/gpu/drm/omapdrm/dss/hdmi5_core.h int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 42 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; wp 50 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); wp 60 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; wp 63 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); wp 147 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c if (hpll->wp->version == 4) wp 162 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) wp 168 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->wp = wp; wp 20 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) wp 22 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) wp 44 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) wp 46 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); wp 49 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) wp 51 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); wp 53 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); wp 56 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) wp 58 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); wp 61 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) wp 63 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); wp 67 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) wp 70 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) wp 74 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); wp 77 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) wp 87 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) wp 90 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); wp 93 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) wp 102 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_video_start(struct hdmi_wp_data *wp) wp 104 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); wp 109 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_video_stop(struct hdmi_wp_data *wp) wp 113 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); wp 115 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); wp 122 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); wp 130 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, wp 135 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, wp 140 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); wp 143 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, wp 153 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); wp 160 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); wp 163 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, wp 178 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (wp->version == 4) wp 184 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); wp 189 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); wp 225 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, wp 232 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); wp 233 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (wp->version == 4) { wp 243 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); wp 246 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, wp 253 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); wp 256 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); wp 258 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); wp 261 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); wp 264 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable) wp 266 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); wp 271 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) wp 273 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); wp 278 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, wp 284 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c wp->base = devm_ioremap_resource(&pdev->dev, res); wp 285 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (IS_ERR(wp->base)) wp 286 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c return PTR_ERR(wp->base); wp 288 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c wp->phys_base = res->start; wp 289 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c wp->version = version; wp 294 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp) wp 296 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c return wp->phys_base + HDMI_WP_AUDIO_DATA; wp 905 drivers/lightnvm/core.c meta->wp = geo->clba; wp 935 drivers/lightnvm/core.c meta->wp += geo->ws_min; wp 943 drivers/lightnvm/core.c meta->wp += geo->ws_min; wp 982 drivers/lightnvm/core.c meta->wp = 0; wp 731 drivers/lightnvm/pblk-init.c chunk->wp = chunk_meta->wp; wp 130 drivers/lightnvm/pblk-recovery.c written_secs += chunk->wp; wp 336 drivers/lightnvm/pblk-recovery.c max_wp = chunk->wp; wp 345 drivers/lightnvm/pblk-recovery.c if (chunk->wp > max_wp || chunk->wp < min_wp) wp 633 drivers/lightnvm/pblk-recovery.c && chunk->wp >= lm->smeta_sec)) wp 1124 drivers/md/dm-zoned-metadata.c zone->wp_block = dmz_sect2blk(blkz->wp - blkz->start); wp 1270 drivers/md/dm-zoned-metadata.c zone->wp_block = dmz_sect2blk(blkz.wp - blkz.start); wp 1284 drivers/md/dm-zoned-metadata.c unsigned int wp = 0; wp 1287 drivers/md/dm-zoned-metadata.c wp = zone->wp_block; wp 1293 drivers/md/dm-zoned-metadata.c dmz_id(zmd, zone), zone->wp_block, wp); wp 1295 drivers/md/dm-zoned-metadata.c if (zone->wp_block < wp) { wp 1297 drivers/md/dm-zoned-metadata.c wp - zone->wp_block); wp 1249 drivers/md/dm.c zone->wp = zone->start + zone->len; wp 1251 drivers/md/dm.c zone->wp = zone->start; wp 1253 drivers/md/dm.c zone->wp = zone->wp + ti->begin - start; wp 243 drivers/media/dvb-core/dvb_frontend.c int wp; wp 252 drivers/media/dvb-core/dvb_frontend.c wp = (events->eventw + 1) % MAX_EVENT; wp 253 drivers/media/dvb-core/dvb_frontend.c if (wp == events->eventr) { wp 262 drivers/media/dvb-core/dvb_frontend.c events->eventw = wp; wp 357 drivers/media/pci/saa7164/saa7164-core.c u32 wp, mcb, rp, cnt = 0; wp 384 drivers/media/pci/saa7164/saa7164-core.c wp = saa7164_readl(port->bufcounter); wp 385 drivers/media/pci/saa7164/saa7164-core.c if (wp > (port->hwcfg.buffercount - 1)) { wp 386 drivers/media/pci/saa7164/saa7164-core.c printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); wp 391 drivers/media/pci/saa7164/saa7164-core.c if (wp == 0) wp 394 drivers/media/pci/saa7164/saa7164-core.c mcb = wp - 1; wp 434 drivers/media/pci/saa7164/saa7164-core.c u32 wp, mcb, rp, cnt = 0; wp 460 drivers/media/pci/saa7164/saa7164-core.c wp = saa7164_readl(port->bufcounter); wp 461 drivers/media/pci/saa7164/saa7164-core.c if (wp > (port->hwcfg.buffercount - 1)) { wp 462 drivers/media/pci/saa7164/saa7164-core.c printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); wp 467 drivers/media/pci/saa7164/saa7164-core.c if (wp == 0) wp 470 drivers/media/pci/saa7164/saa7164-core.c mcb = wp - 1; wp 576 drivers/media/pci/saa7164/saa7164-core.c int wp, i = 0, rp; wp 579 drivers/media/pci/saa7164/saa7164-core.c wp = saa7164_readl(port->bufcounter); wp 580 drivers/media/pci/saa7164/saa7164-core.c if (wp > (port->hwcfg.buffercount - 1)) wp 584 drivers/media/pci/saa7164/saa7164-core.c if (wp == 0) wp 587 drivers/media/pci/saa7164/saa7164-core.c rp = wp - 1; wp 599 drivers/media/pci/saa7164/saa7164-core.c __func__, wp, rp); wp 870 drivers/media/pci/ttpci/av7110_av.c int wp; wp 874 drivers/media/pci/ttpci/av7110_av.c wp = (events->eventw + 1) % MAX_VIDEO_EVENT; wp 875 drivers/media/pci/ttpci/av7110_av.c if (wp == events->eventr) { wp 882 drivers/media/pci/ttpci/av7110_av.c events->eventw = wp; wp 84 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c unsigned long wp, rp; wp 93 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0)); wp 99 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c if (wp < rp) wp 100 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE; wp 102 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c size = wp - rp; wp 115 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c channel->tsin_id, channel, num_packets, buf, pos, rp, wp); wp 127 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE)) wp 131 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0)); wp 57 drivers/media/platform/vicodec/codec-fwht.c s16 *wp = block; wp 68 drivers/media/platform/vicodec/codec-fwht.c *wp = in[x + y * 8]; wp 69 drivers/media/platform/vicodec/codec-fwht.c wp++; wp 121 drivers/media/platform/vicodec/codec-fwht.c s16 *wp = block; wp 150 drivers/media/platform/vicodec/codec-fwht.c *wp++ = 0; wp 155 drivers/media/platform/vicodec/codec-fwht.c *wp++ = 0; wp 156 drivers/media/platform/vicodec/codec-fwht.c *wp++ = coeff; wp 160 drivers/media/platform/vicodec/codec-fwht.c wp = block; wp 167 drivers/media/platform/vicodec/codec-fwht.c dwht_out[x + y * 8] = *wp++; wp 382 drivers/mtd/maps/pcmciamtd.c pr_debug("Region %d, wp = %u\n", i, t->dev[i].wp); wp 1155 drivers/mtd/nand/raw/brcmnand/brcmnand.c static void brcmnand_wp(struct mtd_info *mtd, int wp) wp 1165 drivers/mtd/nand/raw/brcmnand/brcmnand.c if (old_wp != wp) { wp 1166 drivers/mtd/nand/raw/brcmnand/brcmnand.c dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); wp 1167 drivers/mtd/nand/raw/brcmnand/brcmnand.c old_wp = wp; wp 1181 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_set_wp(ctrl, wp); wp 1190 drivers/mtd/nand/raw/brcmnand/brcmnand.c (wp ? 0 : NAND_STATUS_WP), 0); wp 1195 drivers/mtd/nand/raw/brcmnand/brcmnand.c wp ? "on" : "off"); wp 193 drivers/mtd/nand/raw/nandsim.c #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0))) wp 347 drivers/mtd/nand/raw/nandsim.c int wp; /* write Protect */ wp 853 drivers/mtd/nand/raw/nandsim.c struct weak_page *wp; wp 872 drivers/mtd/nand/raw/nandsim.c wp = kzalloc(sizeof(*wp), GFP_KERNEL); wp 873 drivers/mtd/nand/raw/nandsim.c if (!wp) { wp 877 drivers/mtd/nand/raw/nandsim.c wp->page_no = page_no; wp 878 drivers/mtd/nand/raw/nandsim.c wp->max_writes = max_writes; wp 879 drivers/mtd/nand/raw/nandsim.c list_add(&wp->list, &weak_pages); wp 886 drivers/mtd/nand/raw/nandsim.c struct weak_page *wp; wp 888 drivers/mtd/nand/raw/nandsim.c list_for_each_entry(wp, &weak_pages, list) wp 889 drivers/mtd/nand/raw/nandsim.c if (wp->page_no == page_no) { wp 890 drivers/mtd/nand/raw/nandsim.c if (wp->writes_done >= wp->max_writes) wp 892 drivers/mtd/nand/raw/nandsim.c wp->writes_done += 1; wp 1604 drivers/mtd/nand/raw/nandsim.c if (ns->lines.wp) { wp 1644 drivers/mtd/nand/raw/nandsim.c if (ns->lines.wp) { wp 1120 drivers/net/ethernet/chelsio/cxgb3/sge.c struct work_request_hdr *wp = wrp; wp 1160 drivers/net/ethernet/chelsio/cxgb3/sge.c wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo; wp 1161 drivers/net/ethernet/chelsio/cxgb3/sge.c wr_gen2((struct tx_desc *)wp, ogen); wp 166 drivers/net/ethernet/smsc/smc91x.h u16 *wp = (u16 *) p; wp 168 drivers/net/ethernet/smsc/smc91x.h *wp++ = readw(a); wp 173 drivers/net/ethernet/smsc/smc91x.h u16 *wp = (u16 *) p; wp 175 drivers/net/ethernet/smsc/smc91x.h writew(*wp++, a); wp 361 drivers/net/hamradio/baycom_epp.c unsigned char *wp, *bp; wp 374 drivers/net/hamradio/baycom_epp.c wp = bc->hdlctx.buf; wp 379 drivers/net/hamradio/baycom_epp.c *wp++ = 0x7e; wp 400 drivers/net/hamradio/baycom_epp.c *wp++ = bitbuf; wp 408 drivers/net/hamradio/baycom_epp.c *wp++ = bitbuf; wp 413 drivers/net/hamradio/baycom_epp.c bc->hdlctx.bufcnt = wp - bc->hdlctx.buf; wp 300 drivers/net/wireless/realtek/rtlwifi/pci.h static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size) wp 302 drivers/net/wireless/realtek/rtlwifi/pci.h if (rp <= wp) wp 303 drivers/net/wireless/realtek/rtlwifi/pci.h return size - 1 + rp - wp; wp 304 drivers/net/wireless/realtek/rtlwifi/pci.h return rp - wp - 1; wp 873 drivers/net/wireless/realtek/rtw88/mac.c u32 wp, rp; wp 903 drivers/net/wireless/realtek/rtw88/mac.c wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; wp 905 drivers/net/wireless/realtek/rtw88/mac.c h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; wp 198 drivers/net/wireless/realtek/rtw88/pci.c tx_ring->r.wp = 0; wp 288 drivers/net/wireless/realtek/rtw88/pci.c rx_ring->r.wp = 0; wp 404 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; wp 411 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; wp 418 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; wp 425 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; wp 432 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; wp 439 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; wp 446 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; wp 453 drivers/net/wireless/realtek/rtw88/pci.c rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; wp 626 drivers/net/wireless/realtek/rtw88/pci.c else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len)) wp 658 drivers/net/wireless/realtek/rtw88/pci.c if (++ring->r.wp >= ring->r.len) wp 659 drivers/net/wireless/realtek/rtw88/pci.c ring->r.wp = 0; wp 661 drivers/net/wireless/realtek/rtw88/pci.c rtw_write16(rtwdev, bd_idx, ring->r.wp & 0xfff); wp 731 drivers/net/wireless/realtek/rtw88/pci.c if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) { wp 781 drivers/net/wireless/realtek/rtw88/pci.c avail_desc(ring->r.wp, ring->r.rp, ring->r.len) > 4) { wp 832 drivers/net/wireless/realtek/rtw88/pci.c if (cur_wp >= ring->r.wp) wp 833 drivers/net/wireless/realtek/rtw88/pci.c count = cur_wp - ring->r.wp; wp 835 drivers/net/wireless/realtek/rtw88/pci.c count = ring->r.len - (ring->r.wp - cur_wp); wp 884 drivers/net/wireless/realtek/rtw88/pci.c ring->r.wp = cur_wp; wp 130 drivers/net/wireless/realtek/rtw88/pci.h static inline int avail_desc(u32 wp, u32 rp, u32 len) wp 132 drivers/net/wireless/realtek/rtw88/pci.h if (rp > wp) wp 133 drivers/net/wireless/realtek/rtw88/pci.h return rp - wp - 1; wp 135 drivers/net/wireless/realtek/rtw88/pci.h return len - wp + rp - 1; wp 159 drivers/net/wireless/realtek/rtw88/pci.h u32 wp; wp 233 drivers/net/wireless/realtek/rtw88/pci.h buf_desc = ring->r.head + ring->r.wp * size; wp 236 drivers/nvme/host/lightnvm.c __le64 wp; wp 609 drivers/nvme/host/lightnvm.c meta->wp = le64_to_cpu(dev_meta_off->wp); wp 673 drivers/pcmcia/cistpl.c device->dev[i].wp = (*p & 0x08) ? 1 : 0; wp 954 drivers/perf/arm-ccn.c unsigned long wp = hw->config_base; wp 961 drivers/perf/arm-ccn.c hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); wp 966 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); wp 968 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); wp 970 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); wp 972 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); wp 974 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); wp 976 drivers/perf/arm-ccn.c CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); wp 980 drivers/perf/arm-ccn.c writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); wp 982 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); wp 983 drivers/perf/arm-ccn.c writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); wp 985 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); wp 988 drivers/perf/arm-ccn.c writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); wp 990 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); wp 991 drivers/perf/arm-ccn.c writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); wp 993 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); wp 1541 drivers/pinctrl/sh-pfc/pfc-r8a7778.c #define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) wp 1315 drivers/scsi/fcoe/fcoe_ctlr.c struct fip_wwn_desc *wp; wp 1412 drivers/scsi/fcoe/fcoe_ctlr.c wp = (struct fip_wwn_desc *)desc; wp 1413 drivers/scsi/fcoe/fcoe_ctlr.c if (dlen < sizeof(*wp)) wp 1415 drivers/scsi/fcoe/fcoe_ctlr.c if (get_unaligned_be64(&wp->fd_wwn) != fcf->switch_name) wp 866 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c int wp; wp 882 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; wp 884 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); wp 1646 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c int wp; wp 1662 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; wp 1664 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); wp 1027 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c int wp; wp 1043 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; wp 1045 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); wp 174 drivers/scsi/qedf/qedf_fip.c struct fip_wwn_desc *wp; wp 245 drivers/scsi/qedf/qedf_fip.c wp = (struct fip_wwn_desc *)desc; wp 246 drivers/scsi/qedf/qedf_fip.c switch_name = get_unaligned_be64(&wp->fd_wwn); wp 4468 drivers/scsi/scsi_debug.c module_param_named(wp, sdebug_wp, bool, S_IRUGO | S_IWUSR); wp 4528 drivers/scsi/scsi_debug.c MODULE_PARM_DESC(wp, "Write Protect (def=0)"); wp 46 drivers/scsi/sd_zbc.c zone->wp = logical_to_sectors(sdp, get_unaligned_be64(&buf[24])); wp 49 drivers/scsi/sd_zbc.c zone->wp = zone->start + zone->len; wp 2483 drivers/staging/comedi/comedi_fops.c unsigned int wp, n1, n2; wp 2522 drivers/staging/comedi/comedi_fops.c wp = async->buf_write_ptr; wp 2523 drivers/staging/comedi/comedi_fops.c n1 = min(n, async->prealloc_bufsz - wp); wp 2525 drivers/staging/comedi/comedi_fops.c m = copy_from_user(async->prealloc_buf + wp, buf, n1); wp 183 drivers/target/target_core_fabric_configfs.c unsigned long wp; wp 186 drivers/target/target_core_fabric_configfs.c ret = kstrtoul(page, 0, &wp); wp 190 drivers/target/target_core_fabric_configfs.c if ((wp != 1) && (wp != 0)) wp 194 drivers/target/target_core_fabric_configfs.c core_update_device_list_access(lacl->mapped_lun, wp, lacl->se_lun_nacl); wp 199 drivers/target/target_core_fabric_configfs.c se_nacl->initiatorname, lacl->mapped_lun, (wp) ? "ON" : "OFF"); wp 331 drivers/usb/gadget/udc/omap_udc.c u16 *wp; wp 338 drivers/usb/gadget/udc/omap_udc.c wp = (u16 *)buf; wp 340 drivers/usb/gadget/udc/omap_udc.c omap_writew(*wp++, UDC_DATA); wp 343 drivers/usb/gadget/udc/omap_udc.c buf = (u8 *)wp; wp 396 drivers/usb/gadget/udc/omap_udc.c u16 *wp; wp 403 drivers/usb/gadget/udc/omap_udc.c wp = (u16 *)buf; wp 405 drivers/usb/gadget/udc/omap_udc.c *wp++ = omap_readw(UDC_DATA); wp 408 drivers/usb/gadget/udc/omap_udc.c buf = (u8 *)wp; wp 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h struct hdmi_wp_data *wp; wp 277 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_video_start(struct hdmi_wp_data *wp); wp 278 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_video_stop(struct hdmi_wp_data *wp); wp 279 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); wp 280 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); wp 281 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); wp 282 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); wp 283 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); wp 284 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); wp 285 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); wp 286 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, wp 288 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, wp 290 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, wp 294 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); wp 295 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); wp 302 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h struct hdmi_wp_data *wp); wp 318 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); wp 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); wp 320 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, wp 322 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, wp 334 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h struct hdmi_wp_data wp; wp 61 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c struct hdmi_wp_data *wp = data; wp 64 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c irqstatus = hdmi_wp_get_irqstatus(wp); wp 65 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, irqstatus); wp 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); wp 77 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | wp 80 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 82 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); wp 84 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 148 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c struct hdmi_wp_data *wp = &hdmi.wp; wp 156 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_clear_irqenable(wp, 0xffffffff); wp 157 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_irqstatus(wp, 0xffffffff); wp 184 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 188 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); wp 196 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi_wp_video_start(&hdmi.wp); wp 204 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_irqenable(wp, wp 210 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_video_stop(&hdmi.wp); wp 212 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); wp 226 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); wp 230 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_video_stop(&hdmi.wp); wp 232 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); wp 277 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_dump(&hdmi.wp, s); wp 305 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_audio_enable(&hd->wp, true); wp 306 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi4_audio_start(&hd->core, &hd->wp); wp 311 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi4_audio_stop(&hd->core, &hd->wp); wp 312 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_wp_audio_enable(&hd->wp, false); wp 338 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, wp 632 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, wp 657 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), wp 687 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi_wp_init(pdev, &hdmi.wp); wp 691 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); wp 712 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); wp 299 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c struct hdmi_wp_data *wp, struct hdmi_config *cfg) wp 312 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_video_config_timing(wp, &video_timing); wp 317 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_video_config_format(wp, &video_format); wp 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_video_config_interface(wp, &video_timing); wp 676 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 846 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_audio_config_dma(wp, &audio_dma); wp 847 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_audio_config_format(wp, &audio_format); wp 858 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) wp 863 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_audio_core_req_enable(wp, true); wp 868 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) wp 873 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_wp_audio_core_req_enable(wp, false); wp 253 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 258 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); wp 259 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); wp 260 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 65 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c struct hdmi_wp_data *wp = data; wp 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c irqstatus = hdmi_wp_get_irqstatus(wp); wp 69 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_irqstatus(wp, irqstatus); wp 81 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); wp 93 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | wp 96 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 101 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); wp 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); wp 178 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); wp 179 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_irqstatus(&hdmi.wp, wp 180 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_get_irqstatus(&hdmi.wp)); wp 201 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON); wp 205 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); wp 213 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi_wp_video_start(&hdmi.wp); wp 221 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_irqenable(&hdmi.wp, wp 227 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_video_stop(&hdmi.wp); wp 229 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); wp 243 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); wp 247 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_video_stop(&hdmi.wp); wp 249 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); wp 298 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_dump(&hdmi.wp, s); wp 317 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); wp 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); wp 323 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); wp 333 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); wp 334 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_audio_enable(&hd->wp, true); wp 335 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_audio_core_req_enable(&hd->wp, true); wp 340 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_audio_core_req_enable(&hd->wp, false); wp 341 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_wp_audio_enable(&hd->wp, false); wp 342 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); wp 368 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, wp 662 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, wp 688 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), wp 701 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); wp 726 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi_wp_init(pdev, &hdmi.wp); wp 730 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); wp 751 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); wp 589 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 602 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_wp_video_config_timing(wp, &video_timing); wp 607 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_wp_video_config_format(wp, &video_format); wp 609 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_wp_video_config_interface(wp, &video_timing); wp 787 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 876 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_wp_audio_config_dma(wp, &audio_dma); wp 877 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_wp_audio_config_format(wp, &audio_format); wp 287 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.h void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 291 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.h int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, wp 102 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; wp 107 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); wp 117 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; wp 119 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); wp 220 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_wp_data *wp) wp 225 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->wp = wp; wp 21 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) wp 23 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) wp 45 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) wp 47 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); wp 50 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) wp 52 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); wp 54 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); wp 57 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) wp 59 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); wp 62 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) wp 64 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); wp 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) wp 71 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) wp 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); wp 78 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) wp 88 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) wp 91 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); wp 94 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) wp 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_video_start(struct hdmi_wp_data *wp) wp 105 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); wp 110 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_video_stop(struct hdmi_wp_data *wp) wp 114 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); wp 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); wp 123 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); wp 131 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, wp 136 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, wp 141 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); wp 144 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, wp 154 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); wp 159 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); wp 162 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, wp 173 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); wp 178 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); wp 203 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, wp 210 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); wp 223 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); wp 226 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, wp 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); wp 236 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); wp 238 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); wp 241 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); wp 244 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable) wp 246 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); wp 251 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) wp 253 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); wp 258 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) wp 267 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c wp->phys_base = res->start; wp 269 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c wp->base = devm_ioremap_resource(&pdev->dev, res); wp 270 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (IS_ERR(wp->base)) { wp 272 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c return PTR_ERR(wp->base); wp 278 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp) wp 280 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c return wp->phys_base + HDMI_WP_AUDIO_DATA; wp 257 include/linux/lightnvm.h u64 wp; wp 31 include/linux/srcutiny.h void srcu_drive_gp(struct work_struct *wp); wp 107 include/pcmcia/cistpl.h u_char wp; wp 265 include/sound/hdaudio.h unsigned short rp, wp; /* RIRB read/write pointers */ wp 97 include/uapi/linux/blkzoned.h __u64 wp; /* Zone write pointer position */ wp 109 kernel/rcu/srcutiny.c void srcu_drive_gp(struct work_struct *wp) wp 116 kernel/rcu/srcutiny.c ssp = container_of(wp, struct srcu_struct, srcu_work); wp 332 kernel/rcu/tree_exp.h static void sync_rcu_exp_select_node_cpus(struct work_struct *wp) wp 340 kernel/rcu/tree_exp.h container_of(wp, struct rcu_exp_work, rew_work); wp 582 kernel/rcu/tree_exp.h static void wait_rcu_exp_gp(struct work_struct *wp) wp 586 kernel/rcu/tree_exp.h rewp = container_of(wp, struct rcu_exp_work, rew_work); wp 171 lib/inflate.c #define flush_output(w) (wp=(w),flush_window()) wp 610 lib/inflate.c w = wp; /* initialize window position */ wp 691 lib/inflate.c wp = w; /* restore global window pointer */ wp 717 lib/inflate.c w = wp; /* initialize window position */ wp 750 lib/inflate.c wp = w; /* restore global window pointer */ wp 1093 lib/inflate.c wp = 0; wp 1121 lib/inflate.c flush_output(wp); wp 28 lib/mpi/generic_mpih-lshift.c mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt) wp 36 lib/mpi/generic_mpih-lshift.c wp += 1; wp 44 lib/mpi/generic_mpih-lshift.c wp[i] = (high_limb << sh_1) | (low_limb >> sh_2); wp 47 lib/mpi/generic_mpih-lshift.c wp[i] = high_limb << sh_1; wp 29 lib/mpi/generic_mpih-rshift.c mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt) wp 37 lib/mpi/generic_mpih-rshift.c wp -= 1; wp 44 lib/mpi/generic_mpih-rshift.c wp[i] = (low_limb >> sh_1) | (high_limb << sh_2); wp 47 lib/mpi/generic_mpih-rshift.c wp[i] = low_limb >> sh_1; wp 154 lib/mpi/mpi-internal.h mpi_limb_t mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, wp 156 lib/mpi/mpi-internal.h mpi_limb_t mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, wp 134 sound/hda/hdac_bus.c unsigned int wp; wp 140 sound/hda/hdac_bus.c wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE; wp 141 sound/hda/hdac_bus.c bus->unsol_wp = wp; wp 143 sound/hda/hdac_bus.c wp <<= 1; wp 144 sound/hda/hdac_bus.c bus->unsol_queue[wp] = res; wp 145 sound/hda/hdac_bus.c bus->unsol_queue[wp + 1] = res_ex; wp 69 sound/hda/hdac_controller.c bus->rirb.wp = bus->rirb.rp = 0; wp 144 sound/hda/hdac_controller.c unsigned int wp, rp; wp 151 sound/hda/hdac_controller.c wp = snd_hdac_chip_readw(bus, CORBWP); wp 152 sound/hda/hdac_controller.c if (wp == 0xffff) { wp 157 sound/hda/hdac_controller.c wp++; wp 158 sound/hda/hdac_controller.c wp %= AZX_MAX_CORB_ENTRIES; wp 161 sound/hda/hdac_controller.c if (wp == rp) { wp 168 sound/hda/hdac_controller.c bus->corb.buf[wp] = cpu_to_le32(val); wp 169 sound/hda/hdac_controller.c snd_hdac_chip_writew(bus, CORBWP, wp); wp 187 sound/hda/hdac_controller.c unsigned int rp, wp; wp 191 sound/hda/hdac_controller.c wp = snd_hdac_chip_readw(bus, RIRBWP); wp 192 sound/hda/hdac_controller.c if (wp == 0xffff) { wp 197 sound/hda/hdac_controller.c if (wp == bus->rirb.wp) wp 199 sound/hda/hdac_controller.c bus->rirb.wp = wp; wp 201 sound/hda/hdac_controller.c while (bus->rirb.rp != wp) { wp 212 sound/hda/hdac_controller.c res, res_ex, bus->rirb.rp, wp); wp 89 sound/pci/lola/lola.c unsigned int wp = chip->corb.wp + 1; wp 90 sound/pci/lola/lola.c wp %= LOLA_CORB_ENTRIES; wp 91 sound/pci/lola/lola.c chip->corb.wp = wp; wp 92 sound/pci/lola/lola.c chip->corb.buf[wp * 2] = cpu_to_le32(data); wp 93 sound/pci/lola/lola.c chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata); wp 94 sound/pci/lola/lola.c lola_writew(chip, BAR0, CORBWP, wp); wp 112 sound/pci/lola/lola.c unsigned int rp, wp; wp 115 sound/pci/lola/lola.c wp = lola_readw(chip, BAR0, RIRBWP); wp 116 sound/pci/lola/lola.c if (wp == chip->rirb.wp) wp 118 sound/pci/lola/lola.c chip->rirb.wp = wp; wp 120 sound/pci/lola/lola.c while (chip->rirb.rp != wp) { wp 390 sound/pci/lola/lola.c chip->corb.wp = 0; wp 212 sound/pci/lola/lola.h unsigned short rp, wp; /* read/write pointers */ wp 81 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c static bool set_watchpoint(pid_t pid, int size, int wp) wp 83 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c const volatile uint8_t *addr = &var[32 + wp]; wp 112 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c static bool arun_test(int wr_size, int wp_size, int wr, int wp) wp 143 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c if (!set_watchpoint(pid, wp_size, wp)) wp 204 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c int wr, wp, size; wp 216 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c for (wp = wr - size; wp <= wr + size; wp = wp + size) { wp 217 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c result = run_test(size, MIN(size, 8), wr, wp); wp 218 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c if ((result && wr == wp) || wp 219 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c (!result && wr != wp)) wp 222 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c size, wr, wp); wp 226 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c size, wr, wp);