wb_info           373 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dc_writeback_info *wb_info)
wb_info           384 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (wb_info == NULL) {
wb_info           389 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
wb_info           394 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
wb_info           396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
wb_info           404 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
wb_info           405 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			stream->writeback_info[i] = *wb_info;
wb_info           411 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		stream->writeback_info[stream->num_wb_info++] = *wb_info;
wb_info           422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
wb_info           426 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);
wb_info           429 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);
wb_info           339 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc_writeback_info *wb_info);
wb_info          1358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc_writeback_info *wb_info,
wb_info          1365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
wb_info          1366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(wb_info->wb_enabled);
wb_info          1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
wb_info          1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
wb_info          1373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
wb_info          1375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
wb_info          1376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
wb_info          1380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
wb_info          1841 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
wb_info          1847 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
wb_info          1849 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
wb_info          1850 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
wb_info          1851 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
wb_info          1852 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
wb_info          1855 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
wb_info          1856 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
wb_info          1859 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
wb_info          1860 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
wb_info           324 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc_writeback_info *wb_info,
wb_info           328 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc_writeback_info *wb_info,
wb_info           161 drivers/md/md.c 							sizeof(struct wb_info));
wb_info          5782 drivers/md/md.c 						    sizeof(struct wb_info));
wb_info            55 drivers/md/raid1.c 	struct wb_info *wi, *temp_wi;
wb_info            84 drivers/md/raid1.c 	struct wb_info *wi;