vulp 799 arch/alpha/kernel/core_cia.c pyxis_cc = *(vulp)PYXIS_RT_COUNT; vulp 800 arch/alpha/kernel/core_cia.c do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096); vulp 118 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_CONF = 0; vulp 122 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_CONF = 1; vulp 138 arch/alpha/kernel/core_lca.c stat0 = *(vulp)LCA_IOC_STAT0; vulp 139 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_STAT0 = stat0; vulp 146 arch/alpha/kernel/core_lca.c stat0 = *(vulp)LCA_IOC_STAT0; vulp 155 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_STAT0 = stat0; vulp 175 arch/alpha/kernel/core_lca.c stat0 = *(vulp)LCA_IOC_STAT0; vulp 176 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_STAT0 = stat0; vulp 183 arch/alpha/kernel/core_lca.c stat0 = *(vulp)LCA_IOC_STAT0; vulp 192 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_STAT0 = stat0; vulp 245 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_TBIA = 0; vulp 284 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_W_BASE0 = hose->sg_isa->dma_base | (3UL << 32); vulp 285 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_W_MASK0 = (hose->sg_isa->size - 1) & 0xfff00000; vulp 286 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_T_BASE0 = virt_to_phys(hose->sg_isa->ptes); vulp 288 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_W_BASE1 = __direct_map_base | (2UL << 32); vulp 289 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_W_MASK1 = (__direct_map_size - 1) & 0xfff00000; vulp 290 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_T_BASE1 = 0; vulp 292 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_TB_ENA = 0x80; vulp 301 arch/alpha/kernel/core_lca.c *(vulp)LCA_IOC_PAR_DIS = 1UL<<5; vulp 192 arch/alpha/kernel/core_t2.c t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; vulp 193 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg; vulp 227 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = t2_cfg; vulp 244 arch/alpha/kernel/core_t2.c t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; vulp 245 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL; vulp 278 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = t2_cfg; vulp 334 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */ vulp 336 arch/alpha/kernel/core_t2.c *(vulp)T2_WMASK1 = temp; vulp 337 arch/alpha/kernel/core_t2.c *(vulp)T2_TBASE1 = 0; vulp 341 arch/alpha/kernel/core_t2.c __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1); vulp 358 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */ vulp 360 arch/alpha/kernel/core_t2.c *(vulp)T2_WMASK2 = temp; vulp 361 arch/alpha/kernel/core_t2.c *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1; vulp 368 arch/alpha/kernel/core_t2.c __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2); vulp 377 arch/alpha/kernel/core_t2.c printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2); vulp 378 arch/alpha/kernel/core_t2.c printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3); vulp 379 arch/alpha/kernel/core_t2.c printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4); vulp 380 arch/alpha/kernel/core_t2.c printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE); vulp 383 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1); vulp 385 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2); vulp 391 arch/alpha/kernel/core_t2.c t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1; vulp 392 arch/alpha/kernel/core_t2.c t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1; vulp 393 arch/alpha/kernel/core_t2.c t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1; vulp 394 arch/alpha/kernel/core_t2.c t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2; vulp 395 arch/alpha/kernel/core_t2.c t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2; vulp 396 arch/alpha/kernel/core_t2.c t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2; vulp 399 arch/alpha/kernel/core_t2.c t2_saved_config.hae_2 = *(vulp)T2_HAE_2; vulp 400 arch/alpha/kernel/core_t2.c t2_saved_config.hae_3 = *(vulp)T2_HAE_3; vulp 401 arch/alpha/kernel/core_t2.c t2_saved_config.hae_4 = *(vulp)T2_HAE_4; vulp 402 arch/alpha/kernel/core_t2.c t2_saved_config.hbase = *(vulp)T2_HBASE; vulp 421 arch/alpha/kernel/core_t2.c temp = *(vulp)T2_IOCSR; vulp 425 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR = temp | (0x1UL << 26); vulp 427 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR; /* read it back to make sure */ vulp 463 arch/alpha/kernel/core_t2.c *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */ vulp 466 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */ vulp 467 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */ vulp 468 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */ vulp 479 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_4 = 0; mb(); vulp 488 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase; vulp 489 arch/alpha/kernel/core_t2.c *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask; vulp 490 arch/alpha/kernel/core_t2.c *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase; vulp 491 arch/alpha/kernel/core_t2.c *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase; vulp 492 arch/alpha/kernel/core_t2.c *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask; vulp 493 arch/alpha/kernel/core_t2.c *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase; vulp 496 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_1 = srm_hae; vulp 497 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_2 = t2_saved_config.hae_2; vulp 498 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_3 = t2_saved_config.hae_3; vulp 499 arch/alpha/kernel/core_t2.c *(vulp)T2_HAE_4 = t2_saved_config.hae_4; vulp 500 arch/alpha/kernel/core_t2.c *(vulp)T2_HBASE = t2_saved_config.hbase; vulp 502 arch/alpha/kernel/core_t2.c *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */ vulp 510 arch/alpha/kernel/core_t2.c t2_iocsr = *(vulp)T2_IOCSR; vulp 513 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28); vulp 515 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR; /* read it back to make sure */ vulp 518 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28); vulp 520 arch/alpha/kernel/core_t2.c *(vulp)T2_IOCSR; /* read it back to make sure */ vulp 540 arch/alpha/kernel/core_t2.c *(vulp)T2_CERR1 |= *(vulp)T2_CERR1; vulp 541 arch/alpha/kernel/core_t2.c *(vulp)T2_PERR1 |= *(vulp)T2_PERR1; vulp 27 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK = mask; vulp 29 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK; vulp 51 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK = mask; vulp 54 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_REQ = bit; vulp 57 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK; vulp 74 arch/alpha/kernel/irq_pyxis.c pld = *(vulp)PYXIS_INT_REQ; vulp 96 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK = 0; /* disable all */ vulp 97 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_REQ = -1; /* flush all */ vulp 1332 arch/alpha/kernel/setup.c sc_ctl = *(vulp) phys_to_virt (0xfffff000a8UL); vulp 1365 arch/alpha/kernel/setup.c cbox_config = *(vulp) phys_to_virt (0xfffff00008UL); vulp 70 arch/alpha/kernel/sys_miata.c *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */ vulp 71 arch/alpha/kernel/sys_miata.c *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */ vulp 40 arch/alpha/kernel/sys_ruffian.c *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); vulp 41 arch/alpha/kernel/sys_ruffian.c *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ vulp 189 arch/alpha/kernel/sys_ruffian.c bank = *(vulp)bank_addr; vulp 299 arch/alpha/kernel/sys_sable.c *(vulp)T2_AIR = 0x40; vulp 301 arch/alpha/kernel/sys_sable.c *(vulp)T2_AIR; /* re-read to force write */ vulp 303 arch/alpha/kernel/sys_sable.c *(vulp)T2_DIR = mask; vulp 311 arch/alpha/kernel/sys_sable.c *(vulp)T2_VAR = (u_long) bit;