vp_reg_write      297 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, reg_id, val);
vp_reg_write      406 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_SHADOW_UPDATE, VP_SHADOW_UPDATE_ENABLE);
vp_reg_write      554 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
vp_reg_write      557 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
vp_reg_write      560 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
vp_reg_write      561 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_SRC_H_POSITION,
vp_reg_write      563 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
vp_reg_write      564 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
vp_reg_write      567 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2);
vp_reg_write      568 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2);
vp_reg_write      569 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
vp_reg_write      570 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
vp_reg_write      572 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
vp_reg_write      573 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
vp_reg_write      574 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
vp_reg_write      575 drivers/gpu/drm/exynos/exynos_mixer.c 		vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
vp_reg_write      578 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_H_RATIO, state->h_ratio);
vp_reg_write      579 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_V_RATIO, state->v_ratio);
vp_reg_write      581 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
vp_reg_write      584 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_TOP_Y_PTR, luma_addr[0]);
vp_reg_write      585 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_BOT_Y_PTR, luma_addr[1]);
vp_reg_write      586 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_TOP_C_PTR, chroma_addr[0]);
vp_reg_write      587 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]);
vp_reg_write      689 drivers/gpu/drm/exynos/exynos_mixer.c 	vp_reg_write(ctx, VP_SRESET, VP_SRESET_PROCESSING);