vop 42 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_WIN_SET(vop, win, name, v) \ vop 43 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) vop 44 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_SCL_SET(vop, win, name, v) \ vop 45 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) vop 46 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_SCL_SET_EXT(vop, win, name, v) \ vop 47 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win->phy->scl->ext->name, \ vop 50 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ vop 53 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ vop 56 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ vop 59 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ vop 62 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_INTR_SET_MASK(vop, name, mask, v) \ vop 63 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) vop 65 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_REG_SET(vop, group, name, v) \ vop 66 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) vop 68 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_INTR_SET_TYPE(vop, name, type, v) \ vop 71 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->data->intr->nintrs; i++) { \ vop 72 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop->data->intr->intrs[i] & type) { \ vop 77 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_MASK(vop, name, mask, reg); \ vop 79 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_INTR_GET_TYPE(vop, name, type) \ vop 80 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_get_intr_type(vop, &vop->data->intr->name, type) vop 82 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_WIN_GET(vop, win, name) \ vop 83 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_read_reg(vop, win->base, &win->phy->name) vop 88 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_WIN_GET_YRGBADDR(vop, win) \ vop 89 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_readl(vop, win->base + win->phy->yrgb_mst.offset) vop 92 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ((vop_win) - (vop_win)->vop->win) vop 94 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define to_vop(x) container_of(x, struct vop, crtc) vop 117 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop; vop 171 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) vop 173 drivers/gpu/drm/rockchip/rockchip_drm_vop.c writel(v, vop->regs + offset); vop 174 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->regsbak[offset >> 2] = v; vop 177 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) vop 179 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return readl(vop->regs + offset); vop 182 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, vop 185 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; vop 188 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, vop 195 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); vop 206 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t cached_val = vop->regsbak[offset >> 2]; vop 209 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->regsbak[offset >> 2] = v; vop 213 drivers/gpu/drm/rockchip/rockchip_drm_vop.c writel_relaxed(v, vop->regs + offset); vop 215 drivers/gpu/drm/rockchip/rockchip_drm_vop.c writel(v, vop->regs + offset); vop 218 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_get_intr_type(struct vop *vop, vop 222 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t regs = vop_read_reg(vop, 0, reg); vop 224 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->data->intr->nintrs; i++) { vop 225 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) vop 226 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret |= vop->data->intr->intrs[i]; vop 232 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline void vop_cfg_done(struct vop *vop) vop 234 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, cfg_done, 1); vop 310 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, vop 329 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); vop 334 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_x, vop 336 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_y, vop 339 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_x, vop 341 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_y, vop 364 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); vop 367 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); vop 371 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); vop 383 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_x, val); vop 386 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_yrgb_y, val); vop 388 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); vop 389 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); vop 391 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); vop 392 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); vop 393 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); vop 394 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); vop 395 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); vop 399 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_x, val); vop 402 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET(vop, win, scale_cbcr_y, val); vop 404 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); vop 405 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); vop 406 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); vop 407 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); vop 408 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); vop 409 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); vop 410 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); vop 414 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_dsp_hold_valid_irq_enable(struct vop *vop) vop 418 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 421 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 423 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); vop 424 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); vop 426 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 429 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_dsp_hold_valid_irq_disable(struct vop *vop) vop 433 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 436 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 438 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); vop 440 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 465 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static bool vop_line_flag_irq_is_enabled(struct vop *vop) vop 470 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 472 drivers/gpu/drm/rockchip/rockchip_drm_vop.c line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); vop 474 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 479 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_line_flag_irq_enable(struct vop *vop) vop 483 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 486 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 488 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); vop 489 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); vop 491 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 494 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_line_flag_irq_disable(struct vop *vop) vop 498 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 501 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 503 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); vop 505 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 508 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static int vop_core_clks_enable(struct vop *vop) vop 512 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_enable(vop->hclk); vop 516 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_enable(vop->aclk); vop 523 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->hclk); vop 527 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_core_clks_disable(struct vop *vop) vop 529 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->aclk); vop 530 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->hclk); vop 533 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) vop 538 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); vop 539 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); vop 540 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); vop 541 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); vop 544 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, enable, 0); vop 545 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); vop 550 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 553 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = pm_runtime_get_sync(vop->dev); vop 555 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); vop 559 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = vop_core_clks_enable(vop); vop 563 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_enable(vop->dclk); vop 573 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); vop 575 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, vop 580 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 581 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->len; i += 4) vop 582 drivers/gpu/drm/rockchip/rockchip_drm_vop.c writel_relaxed(vop->regsbak[i / 4], vop->regs + i); vop 594 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->data->win_size; i++) { vop 595 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 597 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_win_disable(vop, vop_win); vop 600 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 602 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_cfg_done(vop); vop 607 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->is_enabled = true; vop 609 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 611 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, standby, 1); vop 613 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 620 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->dclk); vop 622 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_core_clks_disable(vop); vop 624 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pm_runtime_put_sync(vop->dev); vop 630 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 633 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 635 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->data->win_size; i++) { vop 636 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 639 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, enable, vop 640 drivers/gpu/drm/rockchip/rockchip_drm_vop.c enabled && (vop->win_enabled & BIT(i))); vop 642 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_cfg_done(vop); vop 644 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 650 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 652 drivers/gpu/drm/rockchip/rockchip_drm_vop.c WARN_ON(vop->event); vop 657 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_lock(&vop->vop_lock); vop 671 drivers/gpu/drm/rockchip/rockchip_drm_vop.c reinit_completion(&vop->dsp_hold_completion); vop 672 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_dsp_hold_valid_irq_enable(vop); vop 674 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 676 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, standby, 1); vop 678 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 680 drivers/gpu/drm/rockchip/rockchip_drm_vop.c wait_for_completion(&vop->dsp_hold_completion); vop 682 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_dsp_hold_valid_irq_disable(vop); vop 684 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->is_enabled = false; vop 689 drivers/gpu/drm/rockchip/rockchip_drm_vop.c rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); vop 691 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->dclk); vop 692 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_core_clks_disable(vop); vop 693 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pm_runtime_put(vop->dev); vop 696 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_unlock(&vop->vop_lock); vop 767 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(old_state->crtc); vop 772 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 774 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_win_disable(vop, vop_win); vop 776 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 787 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(state->crtc); vop 811 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 846 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 848 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, format, format); vop 849 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); vop 850 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); vop 851 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); vop 852 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, y_mir_en, vop 854 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, x_mir_en, vop 869 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); vop 870 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, uv_mst, dma_addr); vop 873 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, vop 881 drivers/gpu/drm/rockchip/rockchip_drm_vop.c scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, vop 885 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, act_info, act_info); vop 886 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, dsp_info, dsp_info); vop 887 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, dsp_st, dsp_st); vop 890 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, rb_swap, rb_swap); vop 900 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, dst_alpha_ctl, vop 907 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, src_alpha_ctl, val); vop 909 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); vop 912 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, enable, 1); vop 913 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->win_enabled |= BIT(win_index); vop 914 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 951 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(plane->state->crtc); vop 964 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop->is_enabled) { vop 966 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 967 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_cfg_done(vop); vop 968 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 981 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_flip_work_queue(&vop->fb_unref_work, old_fb); vop 982 drivers/gpu/drm/rockchip/rockchip_drm_vop.c set_bit(VOP_PENDING_FB_UNREF, &vop->pending); vop 1007 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1010 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 1013 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 1015 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); vop 1016 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); vop 1018 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 1025 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1028 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 1031 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_irqsave(&vop->irq_lock, flags); vop 1033 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); vop 1035 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock_irqrestore(&vop->irq_lock, flags); vop 1042 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1076 drivers/gpu/drm/rockchip/rockchip_drm_vop.c rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); vop 1085 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1086 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const struct vop_data *vop_data = vop->data; vop 1109 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_lock(&vop->vop_lock); vop 1111 drivers/gpu/drm/rockchip/rockchip_drm_vop.c WARN_ON(vop->event); vop 1115 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_unlock(&vop->vop_lock); vop 1116 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); vop 1125 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, pin_pol, pin_pol); vop 1126 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); vop 1130 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, rgb_en, 1); vop 1131 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); vop 1134 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); vop 1135 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, edp_en, 1); vop 1138 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); vop 1139 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, hdmi_en, 1); vop 1142 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); vop 1143 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, mipi_en, 1); vop 1144 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, mipi_dual_channel_en, vop 1149 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); vop 1150 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, output, dp_en, 1); vop 1153 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", vop 1165 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, pre_dither_down, 1); vop 1167 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, pre_dither_down, 0); vop 1170 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); vop 1171 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); vop 1172 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, dither_down_en, 1); vop 1174 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, dither_down_en, 0); vop 1177 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, out_mode, s->output_mode); vop 1179 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); vop 1182 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, hact_st_end, val); vop 1183 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, hpost_st_end, val); vop 1185 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); vop 1188 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, vact_st_end, val); vop 1189 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, modeset, vpost_st_end, val); vop 1191 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); vop 1193 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); vop 1195 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, standby, 0); vop 1196 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_unlock(&vop->vop_lock); vop 1199 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static bool vop_fs_irq_is_pending(struct vop *vop) vop 1201 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return VOP_INTR_GET_TYPE(vop, status, FS_INTR); vop 1204 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_wait_for_irq_handler(struct vop *vop) vop 1217 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, vop 1220 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); vop 1222 drivers/gpu/drm/rockchip/rockchip_drm_vop.c synchronize_irq(vop->irq); vop 1230 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1234 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!vop->is_enabled)) vop 1237 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->reg_lock); vop 1239 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_cfg_done(vop); vop 1241 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->reg_lock); vop 1248 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_wait_for_irq_handler(vop); vop 1253 drivers/gpu/drm/rockchip/rockchip_drm_vop.c WARN_ON(vop->event); vop 1255 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->event = crtc->state->event; vop 1270 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); vop 1271 drivers/gpu/drm/rockchip/rockchip_drm_vop.c set_bit(VOP_PENDING_FB_UNREF, &vop->pending); vop 1320 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static struct drm_connector *vop_get_edp_connector(struct vop *vop) vop 1325 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); vop 1340 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1344 drivers/gpu/drm/rockchip/rockchip_drm_vop.c connector = vop_get_edp_connector(vop); vop 1399 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = container_of(work, struct vop, fb_unref_work); vop 1402 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_crtc_vblank_put(&vop->crtc); vop 1406 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_handle_vblank(struct vop *vop) vop 1408 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_device *drm = vop->drm_dev; vop 1409 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc *crtc = &vop->crtc; vop 1412 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop->event) { vop 1413 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_crtc_send_vblank_event(crtc, vop->event); vop 1415 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->event = NULL; vop 1419 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) vop 1420 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); vop 1425 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = data; vop 1426 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc *crtc = &vop->crtc; vop 1434 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!pm_runtime_get_if_in_use(vop->dev)) vop 1437 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop_core_clks_enable(vop)) { vop 1438 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); vop 1446 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&vop->irq_lock); vop 1448 drivers/gpu/drm/rockchip/rockchip_drm_vop.c active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); vop 1451 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); vop 1453 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&vop->irq_lock); vop 1460 drivers/gpu/drm/rockchip/rockchip_drm_vop.c complete(&vop->dsp_hold_completion); vop 1466 drivers/gpu/drm/rockchip/rockchip_drm_vop.c complete(&vop->line_flag_completion); vop 1473 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_handle_vblank(vop); vop 1480 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", vop 1484 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_core_clks_disable(vop); vop 1486 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pm_runtime_put(vop->dev); vop 1502 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static int vop_create_crtc(struct vop *vop) vop 1504 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const struct vop_data *vop_data = vop->data; vop 1505 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct device *dev = vop->dev; vop 1506 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_device *drm_dev = vop->drm_dev; vop 1508 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc *crtc = &vop->crtc; vop 1519 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 1526 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, vop 1532 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", vop 1558 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 1565 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, vop 1572 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", vop 1582 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", vop 1588 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_flip_work_init(&vop->fb_unref_work, "fb_unref", vop 1591 drivers/gpu/drm/rockchip/rockchip_drm_vop.c init_completion(&vop->dsp_hold_completion); vop 1592 drivers/gpu/drm/rockchip/rockchip_drm_vop.c init_completion(&vop->line_flag_completion); vop 1597 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_DEBUG_KMS(vop->dev, vop 1612 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_destroy_crtc(struct vop *vop) vop 1614 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc *crtc = &vop->crtc; vop 1615 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_device *drm_dev = vop->drm_dev; vop 1639 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_flip_work_cleanup(&vop->fb_unref_work); vop 1642 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static int vop_initial(struct vop *vop) vop 1647 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); vop 1648 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->hclk)) { vop 1649 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); vop 1650 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return PTR_ERR(vop->hclk); vop 1652 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); vop 1653 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->aclk)) { vop 1654 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); vop 1655 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return PTR_ERR(vop->aclk); vop 1657 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); vop 1658 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->dclk)) { vop 1659 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); vop 1660 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return PTR_ERR(vop->dclk); vop 1663 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = pm_runtime_get_sync(vop->dev); vop 1665 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); vop 1669 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_prepare(vop->dclk); vop 1671 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); vop 1676 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_prepare_enable(vop->hclk); vop 1678 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); vop 1682 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = clk_prepare_enable(vop->aclk); vop 1684 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); vop 1691 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ahb_rst = devm_reset_control_get(vop->dev, "ahb"); vop 1693 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); vop 1701 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); vop 1702 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); vop 1704 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->len; i += sizeof(u32)) vop 1705 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); vop 1707 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, misc, global_regdone_en, 1); vop 1708 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_REG_SET(vop, common, dsp_blank, 0); vop 1710 drivers/gpu/drm/rockchip/rockchip_drm_vop.c for (i = 0; i < vop->data->win_size; i++) { vop 1711 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 1715 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); vop 1716 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_win_disable(vop, vop_win); vop 1717 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_WIN_SET(vop, win, gate, 1); vop 1720 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_cfg_done(vop); vop 1725 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); vop 1726 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->dclk_rst)) { vop 1727 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); vop 1728 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = PTR_ERR(vop->dclk_rst); vop 1731 drivers/gpu/drm/rockchip/rockchip_drm_vop.c reset_control_assert(vop->dclk_rst); vop 1733 drivers/gpu/drm/rockchip/rockchip_drm_vop.c reset_control_deassert(vop->dclk_rst); vop 1735 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->hclk); vop 1736 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable(vop->aclk); vop 1738 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->is_enabled = false; vop 1740 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pm_runtime_put_sync(vop->dev); vop 1745 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable_unprepare(vop->aclk); vop 1747 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_disable_unprepare(vop->hclk); vop 1749 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_unprepare(vop->dclk); vop 1751 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pm_runtime_put_sync(vop->dev); vop 1758 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_win_init(struct vop *vop) vop 1760 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const struct vop_data *vop_data = vop->data; vop 1764 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop_win *vop_win = &vop->win[i]; vop 1768 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_win->vop = vop; vop 1787 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = to_vop(crtc); vop 1791 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!crtc || !vop->is_enabled) vop 1794 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_lock(&vop->vop_lock); vop 1800 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop_line_flag_irq_is_enabled(vop)) { vop 1805 drivers/gpu/drm/rockchip/rockchip_drm_vop.c reinit_completion(&vop->line_flag_completion); vop 1806 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_line_flag_irq_enable(vop); vop 1808 drivers/gpu/drm/rockchip/rockchip_drm_vop.c jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, vop 1810 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_line_flag_irq_disable(vop); vop 1813 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); vop 1819 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_unlock(&vop->vop_lock); vop 1829 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop; vop 1838 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), vop 1840 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!vop) vop 1843 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->dev = dev; vop 1844 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->data = vop_data; vop 1845 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->drm_dev = drm_dev; vop 1846 drivers/gpu/drm/rockchip/rockchip_drm_vop.c dev_set_drvdata(dev, vop); vop 1848 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_win_init(vop); vop 1851 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->len = resource_size(res); vop 1852 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->regs = devm_ioremap_resource(dev, res); vop 1853 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->regs)) vop 1854 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return PTR_ERR(vop->regs); vop 1856 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); vop 1857 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!vop->regsbak) vop 1865 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->irq = (unsigned int)irq; vop 1867 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_init(&vop->reg_lock); vop 1868 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock_init(&vop->irq_lock); vop 1869 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mutex_init(&vop->vop_lock); vop 1871 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = vop_create_crtc(vop); vop 1877 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = vop_initial(vop); vop 1884 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = devm_request_irq(dev, vop->irq, vop_isr, vop 1885 drivers/gpu/drm/rockchip/rockchip_drm_vop.c IRQF_SHARED, dev_name(dev), vop); vop 1889 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { vop 1890 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); vop 1891 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (IS_ERR(vop->rgb)) { vop 1892 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = PTR_ERR(vop->rgb); vop 1901 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_destroy_crtc(vop); vop 1907 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct vop *vop = dev_get_drvdata(dev); vop 1909 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (vop->rgb) vop 1910 drivers/gpu/drm/rockchip/rockchip_drm_vop.c rockchip_rgb_fini(vop->rgb); vop 1913 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_destroy_crtc(vop); vop 1915 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_unprepare(vop->aclk); vop 1916 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_unprepare(vop->hclk); vop 1917 drivers/gpu/drm/rockchip/rockchip_drm_vop.c clk_unprepare(vop->dclk); vop 143 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c u8 *vop; vop 153 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6110_ntsc_cif; vop 156 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6110_pal_cif; vop 161 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6010_ntsc_cif; vop 164 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6010_pal_cif; vop 174 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6110_ntsc_d1; vop 177 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6110_pal_d1; vop 182 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6010_ntsc_d1; vop 185 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = vop_6010_pal_d1; vop 191 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c memcpy(solo_enc->vop, vop, vop_len); vop 198 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = solo_enc->vop; vop 201 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[22] = fps >> 4; vop 202 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[23] = ((fps << 4) & 0xf0) | 0x0c vop 204 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[24] = (interval >> 5) & 0xff; vop 205 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[25] = ((interval << 3) & 0xf8) | 0x04; vop 211 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop = solo_enc->jpeg_header; vop 212 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[SOF0_START + 5] = 0xff & (solo_enc->height >> 8); vop 213 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[SOF0_START + 6] = 0xff & solo_enc->height; vop 214 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[SOF0_START + 7] = 0xff & (solo_enc->width >> 8); vop 215 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c vop[SOF0_START + 8] = 0xff & solo_enc->width; vop 217 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c memcpy(vop + DQT_START, vop 744 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_enc->vop, solo_enc->vop_len); vop 163 drivers/media/pci/solo6x10/solo6x10.h u8 vop[64]; vop 2534 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c int hip, mgp, bkp, bep, vip, vop; vop 2562 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c vop = 0; vop 2592 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c vop = 0; vop 2607 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c vop = viq ^ 3; vop 2629 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);