vid_pll_div        41 drivers/clk/meson/vid-pll-div.c static const struct vid_pll_div vid_pll_div_table[] = {
vid_pll_div        61 drivers/clk/meson/vid-pll-div.c static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
vid_pll_div        80 drivers/clk/meson/vid-pll-div.c 	const struct vid_pll_div *div;
vid_pll_div       366 drivers/gpu/drm/meson/meson_vclk.c 	unsigned int vid_pll_div;
vid_pll_div       375 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       384 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       393 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       402 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       411 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       420 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       429 drivers/gpu/drm/meson/meson_vclk.c 		.vid_pll_div = VID_PLL_DIV_5,
vid_pll_div       750 drivers/gpu/drm/meson/meson_vclk.c 			   unsigned int vid_pll_div, unsigned int vclk_div,
vid_pll_div       822 drivers/gpu/drm/meson/meson_vclk.c 	meson_vid_pll_set(priv, vid_pll_div);
vid_pll_div      1044 drivers/gpu/drm/meson/meson_vclk.c 		       params[freq].pll_od3, params[freq].vid_pll_div,