vic 198 arch/s390/kernel/traps.c int si_code, vic; vic 207 arch/s390/kernel/traps.c vic = (current->thread.fpu.fpc & 0xf00) >> 8; vic 208 arch/s390/kernel/traps.c switch (vic) { vic 3354 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->vic = old_stream->timing.vic; vic 3358 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->vic = drm_match_cea_mode(mode_in); vic 2134 drivers/gpu/drm/amd/display/dc/core/dc_resource.c unsigned int vic = pipe_ctx->stream->timing.vic; vic 2302 drivers/gpu/drm/amd/display/dc/core/dc_resource.c vic = 95; vic 2305 drivers/gpu/drm/amd/display/dc/core/dc_resource.c vic = 94; vic 2308 drivers/gpu/drm/amd/display/dc/core/dc_resource.c vic = 93; vic 2311 drivers/gpu/drm/amd/display/dc/core/dc_resource.c vic = 98; vic 2318 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.VIC0_VIC7 = vic; vic 2319 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (vic >= 128) vic 793 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t vic; vic 1495 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int vic; vic 1503 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c vic = drm_match_cea_mode(mode); vic 1504 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || vic 1505 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { vic 1508 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c } else if (vic) { vic 151 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c int vic; vic 1767 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (hdmi->vic == 39) vic 1985 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->vic = drm_match_cea_mode(mode); vic 1987 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!hdmi->vic) { vic 1990 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); vic 1993 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if ((hdmi->vic == 6) || (hdmi->vic == 7) || vic 1994 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c (hdmi->vic == 21) || (hdmi->vic == 22) || vic 1995 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c (hdmi->vic == 2) || (hdmi->vic == 3) || vic 1996 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c (hdmi->vic == 17) || (hdmi->vic == 18)) vic 3000 drivers/gpu/drm/drm_edid.c cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) vic 3020 drivers/gpu/drm/drm_edid.c if (((vic == 8 || vic == 9 || vic 3021 drivers/gpu/drm/drm_edid.c vic == 12 || vic == 13) && mode->vtotal < 263) || vic 3022 drivers/gpu/drm/drm_edid.c ((vic == 23 || vic == 24 || vic 3023 drivers/gpu/drm/drm_edid.c vic == 27 || vic == 28) && mode->vtotal < 314)) { vic 3038 drivers/gpu/drm/drm_edid.c u8 vic; vic 3046 drivers/gpu/drm/drm_edid.c for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { vic 3047 drivers/gpu/drm/drm_edid.c struct drm_display_mode cea_mode = edid_cea_modes[vic]; vic 3060 drivers/gpu/drm/drm_edid.c return vic; vic 3061 drivers/gpu/drm/drm_edid.c } while (cea_mode_alternate_timings(vic, &cea_mode)); vic 3077 drivers/gpu/drm/drm_edid.c u8 vic; vic 3085 drivers/gpu/drm/drm_edid.c for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { vic 3086 drivers/gpu/drm/drm_edid.c struct drm_display_mode cea_mode = edid_cea_modes[vic]; vic 3099 drivers/gpu/drm/drm_edid.c return vic; vic 3100 drivers/gpu/drm/drm_edid.c } while (cea_mode_alternate_timings(vic, &cea_mode)); vic 3107 drivers/gpu/drm/drm_edid.c static bool drm_valid_cea_vic(u8 vic) vic 3109 drivers/gpu/drm/drm_edid.c return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); vic 3146 drivers/gpu/drm/drm_edid.c u8 vic; vic 3151 drivers/gpu/drm/drm_edid.c for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { vic 3152 drivers/gpu/drm/drm_edid.c const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; vic 3164 drivers/gpu/drm/drm_edid.c return vic; vic 3181 drivers/gpu/drm/drm_edid.c u8 vic; vic 3186 drivers/gpu/drm/drm_edid.c for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { vic 3187 drivers/gpu/drm/drm_edid.c const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; vic 3197 drivers/gpu/drm/drm_edid.c return vic; vic 3202 drivers/gpu/drm/drm_edid.c static bool drm_valid_hdmi_vic(u8 vic) vic 3204 drivers/gpu/drm/drm_edid.c return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); vic 3226 drivers/gpu/drm/drm_edid.c u8 vic = drm_match_cea_mode(mode); vic 3229 drivers/gpu/drm/drm_edid.c if (drm_valid_cea_vic(vic)) { vic 3230 drivers/gpu/drm/drm_edid.c cea_mode = &edid_cea_modes[vic]; vic 3233 drivers/gpu/drm/drm_edid.c vic = drm_match_hdmi_mode(mode); vic 3234 drivers/gpu/drm/drm_edid.c if (drm_valid_hdmi_vic(vic)) { vic 3235 drivers/gpu/drm/drm_edid.c cea_mode = &edid_4k_modes[vic]; vic 3295 drivers/gpu/drm/drm_edid.c u8 vic; vic 3301 drivers/gpu/drm/drm_edid.c vic = svd_to_vic(video_db[video_index]); vic 3302 drivers/gpu/drm/drm_edid.c if (!drm_valid_cea_vic(vic)) vic 3305 drivers/gpu/drm/drm_edid.c newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); vic 3333 drivers/gpu/drm/drm_edid.c u8 vic = svd_to_vic(svds[i]); vic 3336 drivers/gpu/drm/drm_edid.c if (!drm_valid_cea_vic(vic)) vic 3339 drivers/gpu/drm/drm_edid.c newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); vic 3342 drivers/gpu/drm/drm_edid.c bitmap_set(hdmi->y420_vdb_modes, vic, 1); vic 3362 drivers/gpu/drm/drm_edid.c u8 vic = svd_to_vic(svd); vic 3365 drivers/gpu/drm/drm_edid.c if (!drm_valid_cea_vic(vic)) vic 3368 drivers/gpu/drm/drm_edid.c bitmap_set(hdmi->y420_cmdb_modes, vic, 1); vic 3465 drivers/gpu/drm/drm_edid.c static int add_hdmi_mode(struct drm_connector *connector, u8 vic) vic 3470 drivers/gpu/drm/drm_edid.c if (!drm_valid_hdmi_vic(vic)) { vic 3471 drivers/gpu/drm/drm_edid.c DRM_ERROR("Unknown HDMI VIC: %d\n", vic); vic 3475 drivers/gpu/drm/drm_edid.c newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); vic 3577 drivers/gpu/drm/drm_edid.c u8 vic; vic 3579 drivers/gpu/drm/drm_edid.c vic = db[9 + offset + i]; vic 3580 drivers/gpu/drm/drm_edid.c modes += add_hdmi_mode(connector, vic); vic 3898 drivers/gpu/drm/drm_edid.c u8 vic; vic 3905 drivers/gpu/drm/drm_edid.c vic = drm_match_cea_mode_clock_tolerance(mode, 5); vic 3906 drivers/gpu/drm/drm_edid.c if (drm_valid_cea_vic(vic)) { vic 3908 drivers/gpu/drm/drm_edid.c cea_mode = &edid_cea_modes[vic]; vic 3912 drivers/gpu/drm/drm_edid.c vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); vic 3913 drivers/gpu/drm/drm_edid.c if (drm_valid_hdmi_vic(vic)) { vic 3915 drivers/gpu/drm/drm_edid.c cea_mode = &edid_4k_modes[vic]; vic 3933 drivers/gpu/drm/drm_edid.c type, vic, mode->clock, clock); vic 5342 drivers/gpu/drm/drm_edid.c u8 vic; vic 5350 drivers/gpu/drm/drm_edid.c vic = drm_match_hdmi_mode(mode); vic 5363 drivers/gpu/drm/drm_edid.c if (vic && s3d_flags) vic 5370 drivers/gpu/drm/drm_edid.c frame->vic = vic; vic 1208 drivers/gpu/drm/drm_modes.c u8 vic = drm_match_cea_mode(mode); vic 1212 drivers/gpu/drm/drm_modes.c if (test_bit(vic, hdmi->y420_vdb_modes)) { vic 2070 drivers/gpu/drm/drm_modes.c u8 vic = drm_match_cea_mode(mode); vic 2072 drivers/gpu/drm/drm_modes.c return test_bit(vic, display->hdmi.y420_vdb_modes); vic 2090 drivers/gpu/drm/drm_modes.c u8 vic = drm_match_cea_mode(mode); vic 2092 drivers/gpu/drm/drm_modes.c return test_bit(vic, display->hdmi.y420_cmdb_modes); vic 374 drivers/gpu/drm/meson/meson_dw_hdmi.c int vic = drm_match_cea_mode(mode); vic 381 drivers/gpu/drm/meson/meson_dw_hdmi.c if (!vic) { vic 393 drivers/gpu/drm/meson/meson_dw_hdmi.c if (meson_venc_hdmi_venc_repeat(vic)) vic 619 drivers/gpu/drm/meson/meson_dw_hdmi.c int vic = drm_match_cea_mode(mode); vic 630 drivers/gpu/drm/meson/meson_dw_hdmi.c if (!vic) { vic 637 drivers/gpu/drm/meson/meson_dw_hdmi.c } else if (!meson_venc_hdmi_supported_vic(vic)) vic 650 drivers/gpu/drm/meson/meson_dw_hdmi.c if (meson_venc_hdmi_venc_repeat(vic)) vic 715 drivers/gpu/drm/meson/meson_dw_hdmi.c int vic = drm_match_cea_mode(mode); vic 717 drivers/gpu/drm/meson/meson_dw_hdmi.c DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); vic 720 drivers/gpu/drm/meson/meson_dw_hdmi.c meson_venc_hdmi_mode_set(priv, vic, mode); vic 818 drivers/gpu/drm/meson/meson_venc.c unsigned int vic; vic 879 drivers/gpu/drm/meson/meson_venc.c bool meson_venc_hdmi_supported_vic(int vic) vic 883 drivers/gpu/drm/meson/meson_venc.c while (vmode->vic && vmode->mode) { vic 884 drivers/gpu/drm/meson/meson_venc.c if (vmode->vic == vic) vic 918 drivers/gpu/drm/meson/meson_venc.c static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) vic 922 drivers/gpu/drm/meson/meson_venc.c while (vmode->vic && vmode->mode) { vic 923 drivers/gpu/drm/meson/meson_venc.c if (vmode->vic == vic) vic 931 drivers/gpu/drm/meson/meson_venc.c bool meson_venc_hdmi_venc_repeat(int vic) vic 934 drivers/gpu/drm/meson/meson_venc.c if (vic == 6 || vic == 7 || /* 480i */ vic 935 drivers/gpu/drm/meson/meson_venc.c vic == 21 || vic == 22 || /* 576i */ vic 936 drivers/gpu/drm/meson/meson_venc.c vic == 17 || vic == 18 || /* 576p */ vic 937 drivers/gpu/drm/meson/meson_venc.c vic == 2 || vic == 3 || /* 480p */ vic 938 drivers/gpu/drm/meson/meson_venc.c vic == 4 || /* 720p60 */ vic 939 drivers/gpu/drm/meson/meson_venc.c vic == 19 || /* 720p50 */ vic 940 drivers/gpu/drm/meson/meson_venc.c vic == 5 || /* 1080i60 */ vic 941 drivers/gpu/drm/meson/meson_venc.c vic == 20) /* 1080i50 */ vic 948 drivers/gpu/drm/meson/meson_venc.c void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, vic 988 drivers/gpu/drm/meson/meson_venc.c if (meson_venc_hdmi_supported_vic(vic)) { vic 989 drivers/gpu/drm/meson/meson_venc.c vmode = meson_venc_hdmi_get_vic_vmode(vic); vic 1003 drivers/gpu/drm/meson/meson_venc.c if (meson_venc_hdmi_venc_repeat(vic)) vic 53 drivers/gpu/drm/meson/meson_venc.h bool meson_venc_hdmi_supported_vic(int vic); vic 54 drivers/gpu/drm/meson/meson_venc.h bool meson_venc_hdmi_venc_repeat(int vic); vic 62 drivers/gpu/drm/meson/meson_venc.h void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, vic 178 drivers/gpu/drm/nouveau/include/nvkm/core/device.h struct nvkm_engine *vic; vic 251 drivers/gpu/drm/nouveau/include/nvkm/core/device.h int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **); vic 2716 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(VIC , device->vic , device->vic); vic 3204 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(NVKM_ENGINE_VIC , vic); vic 425 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c unsigned int vic; vic 449 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c vic = ptr[3]; vic 464 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); vic 31 drivers/gpu/drm/rockchip/inno_hdmi.c int vic; vic 435 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi->hdmi_data.vic = drm_match_cea_mode(mode); vic 440 drivers/gpu/drm/rockchip/inno_hdmi.c if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) || vic 441 drivers/gpu/drm/rockchip/inno_hdmi.c (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) || vic 442 drivers/gpu/drm/rockchip/inno_hdmi.c (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) || vic 443 drivers/gpu/drm/rockchip/inno_hdmi.c (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18)) vic 23 drivers/gpu/drm/rockchip/rk3066_hdmi.c int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ vic 221 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) vic 319 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->hdmi_data.vic = drm_match_cea_mode(mode); vic 322 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || vic 323 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || vic 324 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || vic 325 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) vic 491 drivers/gpu/drm/rockchip/rk3066_hdmi.c u32 vic = drm_match_cea_mode(mode); vic 493 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (vic > 1) vic 46 drivers/gpu/drm/tegra/vic.c static inline struct vic *to_vic(struct tegra_drm_client *client) vic 48 drivers/gpu/drm/tegra/vic.c return container_of(client, struct vic, client); vic 51 drivers/gpu/drm/tegra/vic.c static void vic_writel(struct vic *vic, u32 value, unsigned int offset) vic 53 drivers/gpu/drm/tegra/vic.c writel(value, vic->regs + offset); vic 58 drivers/gpu/drm/tegra/vic.c struct vic *vic = dev_get_drvdata(dev); vic 61 drivers/gpu/drm/tegra/vic.c err = clk_prepare_enable(vic->clk); vic 67 drivers/gpu/drm/tegra/vic.c err = reset_control_deassert(vic->rst); vic 76 drivers/gpu/drm/tegra/vic.c clk_disable_unprepare(vic->clk); vic 82 drivers/gpu/drm/tegra/vic.c struct vic *vic = dev_get_drvdata(dev); vic 85 drivers/gpu/drm/tegra/vic.c err = reset_control_assert(vic->rst); vic 91 drivers/gpu/drm/tegra/vic.c clk_disable_unprepare(vic->clk); vic 93 drivers/gpu/drm/tegra/vic.c vic->booted = false; vic 98 drivers/gpu/drm/tegra/vic.c static int vic_boot(struct vic *vic) vic 104 drivers/gpu/drm/tegra/vic.c if (vic->booted) vic 108 drivers/gpu/drm/tegra/vic.c if (vic->config->supports_sid) { vic 109 drivers/gpu/drm/tegra/vic.c struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); vic 114 drivers/gpu/drm/tegra/vic.c vic_writel(vic, value, VIC_TFBIF_TRANSCFG); vic 119 drivers/gpu/drm/tegra/vic.c vic_writel(vic, value, VIC_THI_STREAMID0); vic 120 drivers/gpu/drm/tegra/vic.c vic_writel(vic, value, VIC_THI_STREAMID1); vic 126 drivers/gpu/drm/tegra/vic.c vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | vic 131 drivers/gpu/drm/tegra/vic.c err = falcon_boot(&vic->falcon); vic 135 drivers/gpu/drm/tegra/vic.c hdr = vic->falcon.firmware.vaddr; vic 137 drivers/gpu/drm/tegra/vic.c hdr = vic->falcon.firmware.vaddr + vic 141 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); vic 142 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, vic 144 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET, vic 145 drivers/gpu/drm/tegra/vic.c (vic->falcon.firmware.paddr + fce_bin_data_offset) vic 148 drivers/gpu/drm/tegra/vic.c err = falcon_wait_idle(&vic->falcon); vic 150 drivers/gpu/drm/tegra/vic.c dev_err(vic->dev, vic 155 drivers/gpu/drm/tegra/vic.c vic->booted = true; vic 187 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(drm); vic 193 drivers/gpu/drm/tegra/vic.c dev_err(vic->dev, "failed to attach to domain: %d\n", vic 198 drivers/gpu/drm/tegra/vic.c vic->domain = tegra->domain; vic 201 drivers/gpu/drm/tegra/vic.c vic->channel = host1x_channel_request(client->dev); vic 202 drivers/gpu/drm/tegra/vic.c if (!vic->channel) { vic 222 drivers/gpu/drm/tegra/vic.c host1x_channel_put(vic->channel); vic 236 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(drm); vic 244 drivers/gpu/drm/tegra/vic.c host1x_channel_put(vic->channel); vic 246 drivers/gpu/drm/tegra/vic.c if (vic->domain) { vic 247 drivers/gpu/drm/tegra/vic.c iommu_detach_group(vic->domain, group); vic 248 drivers/gpu/drm/tegra/vic.c vic->domain = NULL; vic 259 drivers/gpu/drm/tegra/vic.c static int vic_load_firmware(struct vic *vic) vic 263 drivers/gpu/drm/tegra/vic.c if (vic->falcon.data) vic 266 drivers/gpu/drm/tegra/vic.c vic->falcon.data = vic->client.drm; vic 268 drivers/gpu/drm/tegra/vic.c err = falcon_read_firmware(&vic->falcon, vic->config->firmware); vic 272 drivers/gpu/drm/tegra/vic.c err = falcon_load_firmware(&vic->falcon); vic 279 drivers/gpu/drm/tegra/vic.c vic->falcon.data = NULL; vic 286 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(client); vic 289 drivers/gpu/drm/tegra/vic.c err = pm_runtime_get_sync(vic->dev); vic 293 drivers/gpu/drm/tegra/vic.c err = vic_load_firmware(vic); vic 297 drivers/gpu/drm/tegra/vic.c err = vic_boot(vic); vic 301 drivers/gpu/drm/tegra/vic.c context->channel = host1x_channel_get(vic->channel); vic 310 drivers/gpu/drm/tegra/vic.c pm_runtime_put(vic->dev); vic 316 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(context->client); vic 320 drivers/gpu/drm/tegra/vic.c pm_runtime_put(vic->dev); vic 374 drivers/gpu/drm/tegra/vic.c struct vic *vic; vic 377 drivers/gpu/drm/tegra/vic.c vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); vic 378 drivers/gpu/drm/tegra/vic.c if (!vic) vic 381 drivers/gpu/drm/tegra/vic.c vic->config = of_device_get_match_data(dev); vic 393 drivers/gpu/drm/tegra/vic.c vic->regs = devm_ioremap_resource(dev, regs); vic 394 drivers/gpu/drm/tegra/vic.c if (IS_ERR(vic->regs)) vic 395 drivers/gpu/drm/tegra/vic.c return PTR_ERR(vic->regs); vic 397 drivers/gpu/drm/tegra/vic.c vic->clk = devm_clk_get(dev, NULL); vic 398 drivers/gpu/drm/tegra/vic.c if (IS_ERR(vic->clk)) { vic 400 drivers/gpu/drm/tegra/vic.c return PTR_ERR(vic->clk); vic 404 drivers/gpu/drm/tegra/vic.c vic->rst = devm_reset_control_get(dev, "vic"); vic 405 drivers/gpu/drm/tegra/vic.c if (IS_ERR(vic->rst)) { vic 407 drivers/gpu/drm/tegra/vic.c return PTR_ERR(vic->rst); vic 411 drivers/gpu/drm/tegra/vic.c vic->falcon.dev = dev; vic 412 drivers/gpu/drm/tegra/vic.c vic->falcon.regs = vic->regs; vic 413 drivers/gpu/drm/tegra/vic.c vic->falcon.ops = &vic_falcon_ops; vic 415 drivers/gpu/drm/tegra/vic.c err = falcon_init(&vic->falcon); vic 419 drivers/gpu/drm/tegra/vic.c platform_set_drvdata(pdev, vic); vic 421 drivers/gpu/drm/tegra/vic.c INIT_LIST_HEAD(&vic->client.base.list); vic 422 drivers/gpu/drm/tegra/vic.c vic->client.base.ops = &vic_client_ops; vic 423 drivers/gpu/drm/tegra/vic.c vic->client.base.dev = dev; vic 424 drivers/gpu/drm/tegra/vic.c vic->client.base.class = HOST1X_CLASS_VIC; vic 425 drivers/gpu/drm/tegra/vic.c vic->client.base.syncpts = syncpts; vic 426 drivers/gpu/drm/tegra/vic.c vic->client.base.num_syncpts = 1; vic 427 drivers/gpu/drm/tegra/vic.c vic->dev = dev; vic 429 drivers/gpu/drm/tegra/vic.c INIT_LIST_HEAD(&vic->client.list); vic 430 drivers/gpu/drm/tegra/vic.c vic->client.version = vic->config->version; vic 431 drivers/gpu/drm/tegra/vic.c vic->client.ops = &vic_ops; vic 433 drivers/gpu/drm/tegra/vic.c err = host1x_client_register(&vic->client.base); vic 449 drivers/gpu/drm/tegra/vic.c host1x_client_unregister(&vic->client.base); vic 451 drivers/gpu/drm/tegra/vic.c falcon_exit(&vic->falcon); vic 458 drivers/gpu/drm/tegra/vic.c struct vic *vic = platform_get_drvdata(pdev); vic 461 drivers/gpu/drm/tegra/vic.c err = host1x_client_unregister(&vic->client.base); vic 473 drivers/gpu/drm/tegra/vic.c falcon_exit(&vic->falcon); vic 58 drivers/irqchip/irq-aspeed-vic.c static void vic_init_hw(struct aspeed_vic *vic) vic 63 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); vic 64 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); vic 67 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); vic 68 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); vic 71 drivers/irqchip/irq-aspeed-vic.c writel(0, vic->base + AVIC_INT_SELECT); vic 72 drivers/irqchip/irq-aspeed-vic.c writel(0, vic->base + AVIC_INT_SELECT + 4); vic 78 drivers/irqchip/irq-aspeed-vic.c sense = readl(vic->base + AVIC_INT_SENSE); vic 79 drivers/irqchip/irq-aspeed-vic.c vic->edge_sources[0] = ~sense; vic 80 drivers/irqchip/irq-aspeed-vic.c sense = readl(vic->base + AVIC_INT_SENSE + 4); vic 81 drivers/irqchip/irq-aspeed-vic.c vic->edge_sources[1] = ~sense; vic 84 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_EDGE_CLR); vic 85 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4); vic 90 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = system_avic; vic 95 drivers/irqchip/irq-aspeed-vic.c stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS); vic 97 drivers/irqchip/irq-aspeed-vic.c stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4); vic 103 drivers/irqchip/irq-aspeed-vic.c handle_domain_irq(vic->dom, irq, regs); vic 109 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); vic 114 drivers/irqchip/irq-aspeed-vic.c if (vic->edge_sources[sidx] & sbit) vic 115 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); vic 120 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); vic 124 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); vic 129 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); vic 133 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4); vic 139 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = irq_data_get_irq_chip_data(d); vic 144 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); vic 147 drivers/irqchip/irq-aspeed-vic.c if (vic->edge_sources[sidx] & sbit) vic 148 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); vic 162 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic = d->host_data; vic 170 drivers/irqchip/irq-aspeed-vic.c if (vic->edge_sources[sidx] & sbit) vic 174 drivers/irqchip/irq-aspeed-vic.c irq_set_chip_data(irq, vic); vic 188 drivers/irqchip/irq-aspeed-vic.c struct aspeed_vic *vic; vic 199 drivers/irqchip/irq-aspeed-vic.c vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL); vic 200 drivers/irqchip/irq-aspeed-vic.c if (WARN_ON(!vic)) { vic 204 drivers/irqchip/irq-aspeed-vic.c vic->base = regs; vic 207 drivers/irqchip/irq-aspeed-vic.c vic_init_hw(vic); vic 210 drivers/irqchip/irq-aspeed-vic.c system_avic = vic; vic 214 drivers/irqchip/irq-aspeed-vic.c vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0, vic 215 drivers/irqchip/irq-aspeed-vic.c &avic_dom_ops, vic); vic 99 drivers/irqchip/irq-vic.c static void resume_one_vic(struct vic_device *vic) vic 101 drivers/irqchip/irq-vic.c void __iomem *base = vic->base; vic 108 drivers/irqchip/irq-vic.c writel(vic->int_select, base + VIC_INT_SELECT); vic 109 drivers/irqchip/irq-vic.c writel(vic->protect, base + VIC_PROTECT); vic 112 drivers/irqchip/irq-vic.c writel(vic->int_enable, base + VIC_INT_ENABLE); vic 113 drivers/irqchip/irq-vic.c writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); vic 117 drivers/irqchip/irq-vic.c writel(vic->soft_int, base + VIC_INT_SOFT); vic 118 drivers/irqchip/irq-vic.c writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); vic 129 drivers/irqchip/irq-vic.c static void suspend_one_vic(struct vic_device *vic) vic 131 drivers/irqchip/irq-vic.c void __iomem *base = vic->base; vic 135 drivers/irqchip/irq-vic.c vic->int_select = readl(base + VIC_INT_SELECT); vic 136 drivers/irqchip/irq-vic.c vic->int_enable = readl(base + VIC_INT_ENABLE); vic 137 drivers/irqchip/irq-vic.c vic->soft_int = readl(base + VIC_INT_SOFT); vic 138 drivers/irqchip/irq-vic.c vic->protect = readl(base + VIC_PROTECT); vic 143 drivers/irqchip/irq-vic.c writel(vic->resume_irqs, base + VIC_INT_ENABLE); vic 144 drivers/irqchip/irq-vic.c writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); vic 201 drivers/irqchip/irq-vic.c static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) vic 206 drivers/irqchip/irq-vic.c while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { vic 208 drivers/irqchip/irq-vic.c handle_domain_irq(vic->domain, irq, regs); vic 219 drivers/irqchip/irq-vic.c struct vic_device *vic = irq_desc_get_handler_data(desc); vic 223 drivers/irqchip/irq-vic.c while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { vic 225 drivers/irqchip/irq-vic.c generic_handle_irq(irq_find_mapping(vic->domain, hwirq)); vic 1565 drivers/media/i2c/adv7604.c u8 vic = 0; vic 1572 drivers/media/i2c/adv7604.c vic = infoframe_read(sd, 0x04); vic 1574 drivers/media/i2c/adv7604.c if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) && vic 217 drivers/media/v4l2-core/v4l2-dv-timings.c bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic) vic 226 drivers/media/v4l2-core/v4l2-dv-timings.c bt->cea861_vic == vic) { vic 870 drivers/media/v4l2-core/v4l2-dv-timings.c bool is_ce = avi->video_code || (hdmi && hdmi->vic); vic 417 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c unsigned vic; vic 441 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c vic = ptr[3]; vic 456 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); vic 513 drivers/video/hdmi.c else if (frame->vic != 0 || frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) vic 527 drivers/video/hdmi.c if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) vic 600 drivers/video/hdmi.c } else if (frame->vic) { vic 602 drivers/video/hdmi.c ptr[8] = frame->vic; vic 1493 drivers/video/hdmi.c if (hvf->vic == 0 && hvf->s3d_struct == HDMI_3D_STRUCTURE_INVALID) { vic 1498 drivers/video/hdmi.c if (hvf->vic) vic 1499 drivers/video/hdmi.c hdmi_log(" HDMI VIC: %u\n", hvf->vic); vic 1768 drivers/video/hdmi.c hvf->vic = ptr[4]; vic 356 include/linux/hdmi.h u8 vic; vic 109 include/media/v4l2-dv-timings.h bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic);