vgpu_vreg_t 1326 drivers/gpu/drm/i915/gvt/cmd_parser.c stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); vgpu_vreg_t 1327 drivers/gpu/drm/i915/gvt/cmd_parser.c tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & vgpu_vreg_t 1330 drivers/gpu/drm/i915/gvt/cmd_parser.c stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & vgpu_vreg_t 1332 drivers/gpu/drm/i915/gvt/cmd_parser.c tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; vgpu_vreg_t 1351 drivers/gpu/drm/i915/gvt/cmd_parser.c set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), vgpu_vreg_t 1354 drivers/gpu/drm/i915/gvt/cmd_parser.c set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), vgpu_vreg_t 1356 drivers/gpu/drm/i915/gvt/cmd_parser.c set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), vgpu_vreg_t 1359 drivers/gpu/drm/i915/gvt/cmd_parser.c set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), vgpu_vreg_t 1361 drivers/gpu/drm/i915/gvt/cmd_parser.c set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), vgpu_vreg_t 1366 drivers/gpu/drm/i915/gvt/cmd_parser.c vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; vgpu_vreg_t 62 drivers/gpu/drm/i915/gvt/display.c if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) vgpu_vreg_t 77 drivers/gpu/drm/i915/gvt/display.c if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) vgpu_vreg_t 175 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA | vgpu_vreg_t 180 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= vgpu_vreg_t 185 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= vgpu_vreg_t 190 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= vgpu_vreg_t 197 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | vgpu_vreg_t 203 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | vgpu_vreg_t 205 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= vgpu_vreg_t 218 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL1) = vgpu_vreg_t 220 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL1) |= vgpu_vreg_t 222 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, LCPLL1_CTL) = vgpu_vreg_t 224 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); vgpu_vreg_t 231 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; vgpu_vreg_t 232 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t 233 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; vgpu_vreg_t 234 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t 235 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; vgpu_vreg_t 239 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) &= vgpu_vreg_t 241 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 243 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 245 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; vgpu_vreg_t 246 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= vgpu_vreg_t 249 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= vgpu_vreg_t 254 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= vgpu_vreg_t 256 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= vgpu_vreg_t 259 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; vgpu_vreg_t 260 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t 261 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; vgpu_vreg_t 265 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) &= vgpu_vreg_t 267 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 269 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 271 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; vgpu_vreg_t 272 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= vgpu_vreg_t 275 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= vgpu_vreg_t 280 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= vgpu_vreg_t 282 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= vgpu_vreg_t 285 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; vgpu_vreg_t 286 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t 287 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; vgpu_vreg_t 291 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) &= vgpu_vreg_t 293 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 295 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DPLL_CTRL2) |= vgpu_vreg_t 297 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; vgpu_vreg_t 298 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= vgpu_vreg_t 301 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= vgpu_vreg_t 306 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= vgpu_vreg_t 308 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= vgpu_vreg_t 311 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; vgpu_vreg_t 312 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t 313 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; vgpu_vreg_t 319 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; vgpu_vreg_t 324 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= vgpu_vreg_t 327 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; vgpu_vreg_t 329 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; vgpu_vreg_t 334 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; vgpu_vreg_t 338 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; vgpu_vreg_t 339 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; vgpu_vreg_t 340 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; vgpu_vreg_t 341 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; vgpu_vreg_t 344 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; vgpu_vreg_t 453 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; vgpu_vreg_t 502 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SFUSE_STRAP) |= vgpu_vreg_t 504 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; vgpu_vreg_t 506 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SFUSE_STRAP) &= vgpu_vreg_t 508 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; vgpu_vreg_t 510 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; vgpu_vreg_t 511 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= vgpu_vreg_t 128 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; vgpu_vreg_t 130 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; vgpu_vreg_t 162 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; vgpu_vreg_t 163 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; vgpu_vreg_t 169 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; vgpu_vreg_t 171 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; vgpu_vreg_t 198 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; vgpu_vreg_t 199 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; vgpu_vreg_t 247 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; vgpu_vreg_t 259 drivers/gpu/drm/i915/gvt/edid.c vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; vgpu_vreg_t 295 drivers/gpu/drm/i915/gvt/edid.c if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { vgpu_vreg_t 151 drivers/gpu/drm/i915/gvt/fb_decoder.c u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; vgpu_vreg_t 213 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); vgpu_vreg_t 247 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; vgpu_vreg_t 263 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> vgpu_vreg_t 266 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & vgpu_vreg_t 270 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); vgpu_vreg_t 344 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); vgpu_vreg_t 370 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; vgpu_vreg_t 381 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, CURPOS(pipe)); vgpu_vreg_t 387 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); vgpu_vreg_t 388 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); vgpu_vreg_t 423 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); vgpu_vreg_t 474 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; vgpu_vreg_t 485 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & vgpu_vreg_t 488 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); vgpu_vreg_t 496 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); vgpu_vreg_t 500 drivers/gpu/drm/i915/gvt/fb_decoder.c val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); vgpu_vreg_t 1050 drivers/gpu/drm/i915/gvt/gtt.c u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & vgpu_vreg_t 374 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; vgpu_vreg_t 375 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; vgpu_vreg_t 376 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; vgpu_vreg_t 377 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; vgpu_vreg_t 380 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= vgpu_vreg_t 546 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) vgpu_vreg_t 564 drivers/gpu/drm/i915/gvt/handlers.c u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); vgpu_vreg_t 566 drivers/gpu/drm/i915/gvt/handlers.c u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); vgpu_vreg_t 607 drivers/gpu/drm/i915/gvt/handlers.c if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) vgpu_vreg_t 610 drivers/gpu/drm/i915/gvt/handlers.c if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) vgpu_vreg_t 612 drivers/gpu/drm/i915/gvt/handlers.c && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) vgpu_vreg_t 669 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; vgpu_vreg_t 675 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; vgpu_vreg_t 679 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= vgpu_vreg_t 700 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); vgpu_vreg_t 759 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t 761 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; vgpu_vreg_t 763 drivers/gpu/drm/i915/gvt/handlers.c if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) vgpu_vreg_t 781 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t 783 drivers/gpu/drm/i915/gvt/handlers.c if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) vgpu_vreg_t 802 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t 803 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; vgpu_vreg_t 805 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t 1136 drivers/gpu/drm/i915/gvt/handlers.c if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> vgpu_vreg_t 1138 drivers/gpu/drm/i915/gvt/handlers.c unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & vgpu_vreg_t 1163 drivers/gpu/drm/i915/gvt/handlers.c if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> vgpu_vreg_t 1165 drivers/gpu/drm/i915/gvt/handlers.c unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & vgpu_vreg_t 1169 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, SBI_DATA)); vgpu_vreg_t 1418 drivers/gpu/drm/i915/gvt/handlers.c u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); vgpu_vreg_t 1609 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= vgpu_vreg_t 1611 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= vgpu_vreg_t 1616 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= vgpu_vreg_t 1618 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= vgpu_vreg_t 243 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; vgpu_vreg_t 246 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; vgpu_vreg_t 249 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= vgpu_vreg_t 251 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= vgpu_vreg_t 253 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= vgpu_vreg_t 255 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= vgpu_vreg_t 257 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= vgpu_vreg_t 259 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= vgpu_vreg_t 261 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= vgpu_vreg_t 264 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= vgpu_vreg_t 266 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= vgpu_vreg_t 269 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= vgpu_vreg_t 271 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= vgpu_vreg_t 221 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | vgpu_vreg_t 252 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); vgpu_vreg_t 279 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); vgpu_vreg_t 384 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(vgpu, reg) = 0; vgpu_vreg_t 420 drivers/gpu/drm/i915/gvt/mmio_context.c old_v = vgpu_vreg_t(pre, offset); vgpu_vreg_t 424 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, offset); vgpu_vreg_t 438 drivers/gpu/drm/i915/gvt/mmio_context.c old_v = vgpu_vreg_t(pre, l3_offset); vgpu_vreg_t 442 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, l3_offset); vgpu_vreg_t 494 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); vgpu_vreg_t 496 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(pre, mmio->reg) &= vgpu_vreg_t 498 drivers/gpu/drm/i915/gvt/mmio_context.c old_v = vgpu_vreg_t(pre, mmio->reg); vgpu_vreg_t 515 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, mmio->reg) | vgpu_vreg_t 518 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, mmio->reg); vgpu_vreg_t 582 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start; vgpu_vreg_t 831 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; vgpu_vreg_t 832 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; vgpu_vreg_t 42 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; vgpu_vreg_t 43 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; vgpu_vreg_t 44 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; vgpu_vreg_t 45 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; vgpu_vreg_t 47 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; vgpu_vreg_t 48 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; vgpu_vreg_t 49 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; vgpu_vreg_t 51 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = vgpu_vreg_t 53 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = vgpu_vreg_t 55 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = vgpu_vreg_t 57 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = vgpu_vreg_t 60 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); vgpu_vreg_t 62 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX; vgpu_vreg_t 63 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;