vgpu_vreg         875 drivers/gpu/drm/i915/gvt/cmd_parser.c 	vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
vgpu_vreg         940 drivers/gpu/drm/i915/gvt/cmd_parser.c 				vgpu_vreg(vgpu, offset) = data;
vgpu_vreg          67 drivers/gpu/drm/i915/gvt/debugfs.c 	vreg = vgpu_vreg(param->vgpu, offset);
vgpu_vreg          40 drivers/gpu/drm/i915/gvt/display.c 	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
vgpu_vreg          65 drivers/gpu/drm/i915/gvt/display.c 	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
vgpu_vreg         141 drivers/gpu/drm/i915/gvt/edid.c 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
vgpu_vreg         143 drivers/gpu/drm/i915/gvt/edid.c 	pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
vgpu_vreg         182 drivers/gpu/drm/i915/gvt/edid.c 	if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
vgpu_vreg         184 drivers/gpu/drm/i915/gvt/edid.c 			vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
vgpu_vreg         237 drivers/gpu/drm/i915/gvt/edid.c 			if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
vgpu_vreg         271 drivers/gpu/drm/i915/gvt/edid.c 		vgpu_vreg(vgpu, offset) = wvalue;
vgpu_vreg         297 drivers/gpu/drm/i915/gvt/edid.c 			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
vgpu_vreg         308 drivers/gpu/drm/i915/gvt/edid.c 		memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
vgpu_vreg         309 drivers/gpu/drm/i915/gvt/edid.c 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
vgpu_vreg         330 drivers/gpu/drm/i915/gvt/edid.c 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
vgpu_vreg         339 drivers/gpu/drm/i915/gvt/edid.c 	u32 value = vgpu_vreg(vgpu, offset);
vgpu_vreg         341 drivers/gpu/drm/i915/gvt/edid.c 	if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
vgpu_vreg         342 drivers/gpu/drm/i915/gvt/edid.c 		vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
vgpu_vreg         353 drivers/gpu/drm/i915/gvt/edid.c 		vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
vgpu_vreg         382 drivers/gpu/drm/i915/gvt/edid.c 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
vgpu_vreg         414 drivers/gpu/drm/i915/gvt/edid.c 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
vgpu_vreg         484 drivers/gpu/drm/i915/gvt/edid.c 		vgpu_vreg(vgpu, offset) = value;
vgpu_vreg         490 drivers/gpu/drm/i915/gvt/edid.c 	msg = vgpu_vreg(vgpu, offset + 4);
vgpu_vreg         501 drivers/gpu/drm/i915/gvt/edid.c 	vgpu_vreg(vgpu, offset) =
vgpu_vreg         551 drivers/gpu/drm/i915/gvt/edid.c 	vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
vgpu_vreg         100 drivers/gpu/drm/i915/gvt/execlist.c 	status.ldw = vgpu_vreg(vgpu, status_reg);
vgpu_vreg         101 drivers/gpu/drm/i915/gvt/execlist.c 	status.udw = vgpu_vreg(vgpu, status_reg + 4);
vgpu_vreg         119 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, status_reg) = status.ldw;
vgpu_vreg         120 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, status_reg + 4) = status.udw;
vgpu_vreg         143 drivers/gpu/drm/i915/gvt/execlist.c 	ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
vgpu_vreg         156 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, offset) = status->ldw;
vgpu_vreg         157 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, offset + 4) = status->udw;
vgpu_vreg         160 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
vgpu_vreg         269 drivers/gpu/drm/i915/gvt/execlist.c 	status.ldw = vgpu_vreg(vgpu, status_reg);
vgpu_vreg         270 drivers/gpu/drm/i915/gvt/execlist.c 	status.udw = vgpu_vreg(vgpu, status_reg + 4);
vgpu_vreg         523 drivers/gpu/drm/i915/gvt/execlist.c 	ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
vgpu_vreg         526 drivers/gpu/drm/i915/gvt/execlist.c 	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
vgpu_vreg          75 drivers/gpu/drm/i915/gvt/handlers.c 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
vgpu_vreg          81 drivers/gpu/drm/i915/gvt/handlers.c 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
vgpu_vreg         283 drivers/gpu/drm/i915/gvt/handlers.c 	old = vgpu_vreg(vgpu, offset);
vgpu_vreg         306 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = new;
vgpu_vreg         307 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
vgpu_vreg         318 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg         351 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = 0;
vgpu_vreg         373 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
vgpu_vreg         391 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
vgpu_vreg         392 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
vgpu_vreg         394 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
vgpu_vreg         403 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
vgpu_vreg         404 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
vgpu_vreg         406 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
vgpu_vreg         408 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
vgpu_vreg         409 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
vgpu_vreg         411 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
vgpu_vreg         424 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = 1 << 17;
vgpu_vreg         427 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = 0x3;
vgpu_vreg         430 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = 0x2f << 16;
vgpu_vreg         446 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg         449 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
vgpu_vreg         451 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
vgpu_vreg         541 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
vgpu_vreg         542 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
vgpu_vreg         544 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
vgpu_vreg         555 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
vgpu_vreg         565 drivers/gpu/drm/i915/gvt/handlers.c 	u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
vgpu_vreg         697 drivers/gpu/drm/i915/gvt/handlers.c 	data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
vgpu_vreg         714 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
vgpu_vreg         715 drivers/gpu/drm/i915/gvt/handlers.c 		(vgpu_vreg(vgpu, offset) & sticky_mask);
vgpu_vreg         716 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
vgpu_vreg         726 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg         729 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
vgpu_vreg         739 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg         742 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
vgpu_vreg         744 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
vgpu_vreg         759 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg         781 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg         802 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg         805 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg         808 drivers/gpu/drm/i915/gvt/handlers.c 	if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
vgpu_vreg         855 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, reg) = value;
vgpu_vreg         917 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg         931 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = 0;
vgpu_vreg         939 drivers/gpu/drm/i915/gvt/handlers.c 	msg = vgpu_vreg(vgpu, offset + 4);
vgpu_vreg         959 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
vgpu_vreg         976 drivers/gpu/drm/i915/gvt/handlers.c 			u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
vgpu_vreg         998 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset + 4) = 0;
vgpu_vreg        1017 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 4) = 0;
vgpu_vreg        1018 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 8) = 0;
vgpu_vreg        1019 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 12) = 0;
vgpu_vreg        1020 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 16) = 0;
vgpu_vreg        1021 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 20) = 0;
vgpu_vreg        1030 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset + 4 * idx) = 0;
vgpu_vreg        1052 drivers/gpu/drm/i915/gvt/handlers.c 					vgpu_vreg(vgpu, offset +
vgpu_vreg        1085 drivers/gpu/drm/i915/gvt/handlers.c 	vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
vgpu_vreg        1140 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
vgpu_vreg        1153 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg        1161 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = data;
vgpu_vreg        1319 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) &
vgpu_vreg        1321 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |=
vgpu_vreg        1324 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &=
vgpu_vreg        1334 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
vgpu_vreg        1335 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
vgpu_vreg        1337 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
vgpu_vreg        1347 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
vgpu_vreg        1348 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
vgpu_vreg        1358 drivers/gpu/drm/i915/gvt/handlers.c 	mode = vgpu_vreg(vgpu, offset);
vgpu_vreg        1396 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
vgpu_vreg        1399 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
vgpu_vreg        1402 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
vgpu_vreg        1405 drivers/gpu/drm/i915/gvt/handlers.c 	if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
vgpu_vreg        1408 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1521 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1534 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1547 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1560 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
vgpu_vreg        1563 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
vgpu_vreg        1564 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
vgpu_vreg        1568 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1576 drivers/gpu/drm/i915/gvt/handlers.c 	u32 v = vgpu_vreg(vgpu, offset);
vgpu_vreg        1580 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1591 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset - 0x600) = v;
vgpu_vreg        1592 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset - 0x800) = v;
vgpu_vreg        1594 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset - 0x400) = v;
vgpu_vreg        1595 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset - 0x600) = v;
vgpu_vreg        1598 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1623 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = v;
vgpu_vreg        1631 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = 0;
vgpu_vreg        1657 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
vgpu_vreg        1752 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = 0;
vgpu_vreg        1784 drivers/gpu/drm/i915/gvt/handlers.c 	data = vgpu_vreg(vgpu, offset);
vgpu_vreg        1791 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = data;
vgpu_vreg        3480 drivers/gpu/drm/i915/gvt/handlers.c 	old_vreg = vgpu_vreg(vgpu, offset);
vgpu_vreg        3482 drivers/gpu/drm/i915/gvt/handlers.c 	mask = vgpu_vreg(vgpu, offset) >> 16;
vgpu_vreg        3483 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
vgpu_vreg        3484 drivers/gpu/drm/i915/gvt/handlers.c 				(vgpu_vreg(vgpu, offset) & mask);
vgpu_vreg        3557 drivers/gpu/drm/i915/gvt/handlers.c 			old_vreg = vgpu_vreg(vgpu, offset);
vgpu_vreg        3569 drivers/gpu/drm/i915/gvt/handlers.c 			data |= vgpu_vreg(vgpu, offset) & ro_mask;
vgpu_vreg        3575 drivers/gpu/drm/i915/gvt/handlers.c 			u32 mask = vgpu_vreg(vgpu, offset) >> 16;
vgpu_vreg        3577 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
vgpu_vreg        3578 drivers/gpu/drm/i915/gvt/handlers.c 					| (vgpu_vreg(vgpu, offset) & mask);
vgpu_vreg         182 drivers/gpu/drm/i915/gvt/interrupt.c 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
vgpu_vreg         183 drivers/gpu/drm/i915/gvt/interrupt.c 		       (vgpu_vreg(vgpu, reg) ^ imr));
vgpu_vreg         185 drivers/gpu/drm/i915/gvt/interrupt.c 	vgpu_vreg(vgpu, reg) = imr;
vgpu_vreg         211 drivers/gpu/drm/i915/gvt/interrupt.c 	u32 virtual_ier = vgpu_vreg(vgpu, reg);
vgpu_vreg         223 drivers/gpu/drm/i915/gvt/interrupt.c 	vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
vgpu_vreg         224 drivers/gpu/drm/i915/gvt/interrupt.c 	vgpu_vreg(vgpu, reg) |= ier;
vgpu_vreg         252 drivers/gpu/drm/i915/gvt/interrupt.c 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
vgpu_vreg         253 drivers/gpu/drm/i915/gvt/interrupt.c 		       (vgpu_vreg(vgpu, reg) ^ ier));
vgpu_vreg         255 drivers/gpu/drm/i915/gvt/interrupt.c 	vgpu_vreg(vgpu, reg) = ier;
vgpu_vreg         289 drivers/gpu/drm/i915/gvt/interrupt.c 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
vgpu_vreg         290 drivers/gpu/drm/i915/gvt/interrupt.c 		       (vgpu_vreg(vgpu, reg) ^ iir));
vgpu_vreg         295 drivers/gpu/drm/i915/gvt/interrupt.c 	vgpu_vreg(vgpu, reg) &= ~iir;
vgpu_vreg         328 drivers/gpu/drm/i915/gvt/interrupt.c 	u32 val = vgpu_vreg(vgpu,
vgpu_vreg         330 drivers/gpu/drm/i915/gvt/interrupt.c 		& vgpu_vreg(vgpu,
vgpu_vreg         359 drivers/gpu/drm/i915/gvt/interrupt.c 		vgpu_vreg(vgpu, isr) &= ~clear_bits;
vgpu_vreg         360 drivers/gpu/drm/i915/gvt/interrupt.c 		vgpu_vreg(vgpu, isr) |= set_bits;
vgpu_vreg         367 drivers/gpu/drm/i915/gvt/interrupt.c 		vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
vgpu_vreg         414 drivers/gpu/drm/i915/gvt/interrupt.c 	if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
vgpu_vreg         417 drivers/gpu/drm/i915/gvt/interrupt.c 		set_bit(bit, (void *)&vgpu_vreg(vgpu,
vgpu_vreg         469 drivers/gpu/drm/i915/gvt/interrupt.c 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
vgpu_vreg         481 drivers/gpu/drm/i915/gvt/interrupt.c 		if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
vgpu_vreg         482 drivers/gpu/drm/i915/gvt/interrupt.c 				& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
vgpu_vreg         486 drivers/gpu/drm/i915/gvt/interrupt.c 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
vgpu_vreg         219 drivers/gpu/drm/i915/gvt/scheduler.c 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
vgpu_vreg         221 drivers/gpu/drm/i915/gvt/scheduler.c 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
vgpu_vreg         223 drivers/gpu/drm/i915/gvt/scheduler.c 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);