vcpu_read_sys_reg 384 arch/arm64/include/asm/kvm_emulate.h return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; vcpu_read_sys_reg 406 arch/arm64/include/asm/kvm_emulate.h u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); vcpu_read_sys_reg 417 arch/arm64/include/asm/kvm_emulate.h return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25)); vcpu_read_sys_reg 388 arch/arm64/include/asm/kvm_host.h u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); vcpu_read_sys_reg 307 arch/arm64/include/asm/kvm_mmu.h return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; vcpu_read_sys_reg 38 arch/arm64/kvm/debug.c u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1); vcpu_read_sys_reg 53 arch/arm64/kvm/debug.c vcpu_read_sys_reg(vcpu, MDSCR_EL1)); vcpu_read_sys_reg 149 arch/arm64/kvm/debug.c mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); vcpu_read_sys_reg 153 arch/arm64/kvm/debug.c mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); vcpu_read_sys_reg 171 arch/arm64/kvm/debug.c mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); vcpu_read_sys_reg 197 arch/arm64/kvm/debug.c if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE)) vcpu_read_sys_reg 205 arch/arm64/kvm/debug.c trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1)); vcpu_read_sys_reg 47 arch/arm64/kvm/inject_fault.c return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type; vcpu_read_sys_reg 64 arch/arm64/kvm/inject_fault.c unsigned long sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); vcpu_read_sys_reg 221 arch/arm64/kvm/sys_regs.c val = vcpu_read_sys_reg(vcpu, reg); vcpu_read_sys_reg 390 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, r->reg); vcpu_read_sys_reg 1292 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, reg); vcpu_read_sys_reg 1304 arch/arm64/kvm/sys_regs.c csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); vcpu_read_sys_reg 30 arch/arm64/kvm/sys_regs_generic_v8.c p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);